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  • University of Washington
  • Seattle, WA, 98105

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  1. bespoke-silicon-group/bsg_manycore bespoke-silicon-group/bsg_manycore Public

    Tile based architecture designed for computing efficiency, scalability and generality

    SystemVerilog 226 58

  2. bespoke-silicon-group/basejump_stl bespoke-silicon-group/basejump_stl Public

    BaseJump STL: A Standard Template Library for SystemVerilog

    SystemVerilog 513 98

  3. bsg-external/HardFloat bsg-external/HardFloat Public

    C++ 8 7

  4. CNN-Digit-Recognition-Accelerated-on-FPGA CNN-Digit-Recognition-Accelerated-on-FPGA Public

    A CNN-based hardware digit/image recognition module designed on PyTorch and then implemented with Verilog on FPGA

    Verilog 13

  5. SHA_SM3_SM4-Encryption-Algorithm SHA_SM3_SM4-Encryption-Algorithm Public

    With basic SM3 & SM4 Encryption IP implemented with both Verilog and C , along with package for switching between SHA and SM3

    C 5 1

  6. Backend-of-the-MES-Design Backend-of-the-MES-Design Public

    Backend part of the Intelligent Workshop project with Java, with basic CRUD, authority management and information maintenance modules, and product quality data analysis mapper & controller

    Java 8