v0.24.4

PowerNetworkMatrices v0.24.4

Diff since v0.24.3

Merged pull requests:

• add icd to ybus build (#298) (@m-bossart)
• Reorganize docs, add info, reduce redundancies (#337) (@acostarelli)
• Jd/transformer refactor part 1 (#339) (@jd-lara)
• multi ref bus (#340) (@jd-lara)
• psy6 updates for arc_admittance performance and multi-ref (#343) (@m-bossart)
• Add docs deploy concurrency guard and Sienna aggregate refresh dispatch. (#345) (@kdayday)
• Key contingencies by IS id; read the system UUID from PSY (#347) (@jd-lara)
• Various network-reduction fixes (#348) (@m-bossart)
• Mb/network flow (#350) (@m-bossart)
• Resolve nested reduction aggregates through one leaf walk (#351) (@luke-kiernan)
• feat: expose a chain's segment orientations, replacing _get_chain_data (#353) (@jd-lara)
• Name mixed-group leaves with PNM's get_name, not PSY's (#354) (@luke-kiernan)
• Name reduced arcs for the arc, not for their members (#356) (@luke-kiernan)
• Give a reduced arc one identity, keyed by the arc (#357) (@luke-kiernan)
• Lk/arc derived entry names (#359) (@jd-lara)
• Let reverse indexing defer to the forward filter verdict (#360) (@luke-kiernan)
• Lk/arc derived entry names (#361) (@jd-lara)
• fix pin irreducible buses bug (#362) (@m-bossart)
• Guard the component name index against the forward/reverse filter asymmetry (#363) (@luke-kiernan)
• Made DC path respect minimum reactance (#364) (@m-bossart)
• Follow the DeviceBaseUnit -> ComponentBaseUnit rename (#365) (@luke-kiernan)
• Pin co-developed dependencies to the OpenAPI.jl 1.x branches (#366) (@jd-lara)
• fix: resolve transitive protected-bus merging in zero-impedance reduction (#367) (@mcllerena)
• handle self-loops in zero impedance reduction (#368) (@m-bossart)
• Support outage of phase shifting branches in MODF (#370) (@m-bossart)
• test fix for julia 1.13 (#371) (@m-bossart)
• Follow IS's move to EnumX (#372) (@luke-kiernan)
• Jd/psy6 correctness (#373) (@jd-lara)
• sort before partition (#376) (@m-bossart)
• get ratings in system pu (#377) (@m-bossart)
• Pass input_basis to bus keyword constructors (PowerSystems.jl#1823 fallout) (#378) (@luke-kiernan)
• Make in-place Ybus modifications exact, update the DC susceptance, and fix negative-reactance outages (#379) (@jd-lara)
• Add LinearSolverCache abstract supertype for factorization caches (#381) (@luke-kiernan)
• Add LeanLU static-pivot refactorization to KLUWrapper (#382) (@luke-kiernan)
• Lock-free KLU and lean static-pivot LU (no changes left; keeps the stack linked) (#384) (@jd-lara)
• Add worker cores, dense-free virtual queries, bridge labels and a faster BranchCatalog (#386) (@jd-lara)
• arc subnetwork axis bug fix (#390) (@jd-lara)
• Add complex AppleAccelerate and MKL Pardiso factor caches (#391) (@jd-lara)
• Fix warning regex in zero-impedance irreducible bus test (#394) (@jd-lara)

Closed issues:

• Improve computation of virtual LODF matrix (#42)
• sparsify is very slow (#62)
• Incorporate Impedance Correction Tables in Ybus (#196)
• Y bus mismatch vs. PSS(e) on modified WECC 240 case (#215)
• Handle PhaseShiftingTransformers in Parallel (#231)
• Cleanup Documentation for Diataxis (#292)
• Bug: Branch silently dropped from NetworkReductionData when a PhaseShiftingTransformer is parallel to a regular branch (#305)
• Remaining ZIL discrepancies vs PSSE (#335)
• BranchCatalog: make the arc the identity, not the synthesized name (#352)
• Use StringTemplates in Arc Names (#358)
• arc_subnetwork_axis keeps pre-merge arc labels after a bus merge (#369)
• ABA factorization is KLU-only, and VirtualPTDF has no copy-free cached row accessor (#375)
• Add a complex AppleAccelerate factorization cache (#389)