v0.8-prebuilt

Prebuilt release from commit bd1d96e. Linux aarch64 native engine plus flashable XIAO ESP32S3 Plus image (DIO flash mode, 16 MB).

Since v0.7: USB serial hardening (book moves carry a pv line so a dropped byte stays repairable; wrapper repair policy plus auto-reset; honest baud message), 64-byte data cache lines for about 4 percent more board node throughput.

Gates: desktop unit suite 18/18; board bench about 15.0k nps warm; 3-game board-vs-native gate clean. Strength total remains about +242 Elo vs Tier-1.

Flash: unzip board-flash.zip, then from inside it run python -m esptool --port /dev/ttyACM0 write_flash "@flash_args".

v0.7-prebuilt

Prebuilt release from commit 7f95313. Linux aarch64 native engine plus flashable XIAO ESP32S3 Plus image (DIO flash mode, 16 MB).

Since v0.6: UCI clock-parser hardening (float or zero clocks no longer hang the board), illegal-FEN guard (no more abort on corrupt positions), EPD suite fixes, adaptive time-policy hill-climb audited and reverted to parity defaults.

Gates: desktop unit suite 18/18; v07 vs v06 200 games at 2+0.02 scored 55-40-105 (+26.1 +/- 33.2, LOS 93.8%, zero forfeits); board bench 14,315 nps warm; 3-game board-vs-native gate clean. Strength total remains about +242 Elo vs Tier-1.

Flash: unzip board-flash.zip, then from inside it run python -m esptool --port /dev/ttyACM0 write_flash "@flash_args".

v0.6-prebuilt

Prebuilt release from commit 0358fb8. Includes the Linux aarch64 native engine and a flashable XIAO ESP32S3 Plus image. The board image is configured for DIO flash mode. Since v0.5: C9 square-major weight layout (+6.9 Elo, board bench 14.2k cool), C11 128KB SRAM L0 TT (+5.2 Elo), web pause/resume, async multi-device moves, Thinking loader, front-end polish. Strength total ~+242 Elo vs Tier-1.

v0.5-prebuilt

Prebuilt release from commit 1efb667. Includes the Linux aarch64 native engine and a flashable XIAO ESP32S3 Plus image. The board image is configured for DIO flash mode.

v0.4-prebuilt

Prebuilt release from commit 1d38015. Includes the Linux aarch64 native engine and a flashable XIAO ESP32S3 Plus image. The board image is configured for DIO flash mode.

v0.3-prebuilt

Output-layer staging + board test-suite fix, commit 4749c02.

What changed since v0.2-prebuilt

• Board: +6% node throughput. The evaluator's 1 KB of output weights+bias now stage into internal SRAM at boot (was read through flash XIP on every eval). Bit-exact everywhere by construction; same-session A/B measured 18.8k vs 17.7k nps (cool board) and 15.5k vs 14.6k (hot board). Design notes: docs/output-layer-staging.md.
• Board: console test-suite abort fixed. Since the web phases landed, running the self-test aborted at t=9.1 s on every firmware variant (internal SRAM could no longer fit the suite's 96 KB stack churn). Pthread default is now 16 KB, searchers get an explicit 28 KB block, and thread-creation failures degrade gracefully instead of rebooting. The suite now runs past the old abort point into its normal >1 h perft tail.
• Desktop: bit-exact with v0.2. Bench node count identical (7,582,143 across 90 FENs at depth 10); unit gate 18/18. No strength change on desktop by design; on-device value of the speedup extrapolates to roughly +10-15 Elo via the paired-fused throughput curve.

Contents

• Dog-native - Linux aarch64 UCI engine, built from a clean checkout of 4749c02. md5 ed49d5fefa02e6654d8cc8cff940eb19. Bench: 7,582,143 nodes (deterministic).
• board-flash.zip - XIAO ESP32-S3 firmware image set (dio/80m/16MB): flash_args, bootloader, partition table, OTA data, app (esp32chesstest.bin), SPIFFS. Flash from the zip root:
  python -m esptool --chip esp32s3 -p PORT -b 460800 --before default_reset --after hard_reset write_flash @flash_args

Board gates on this firmware: bench ladder consistent, board-vs-native games clean (no stalls/forfeits/illegal moves), 2-thread UCI smoke clean, boot-time kernel selftests passing.

Prebuilt binaries - paired-fused state (+174 Elo on board)

Paired-fused evaluator state, commit 31be6d3.

What changed since v0.1-prebuilt

• Board: ~1.8x node throughput. Startpos console bench went from ~8,300 to ~14,700 average nps (~17k instantaneous), worth a measured +174 +/- 34 Elo on-device (240-game asymmetric-clock selfplay). Fixed-depth searches now match the desktop binary digit-for-digit through depth 8.
• The evaluator was rebuilt (paired weight-row layout, fused dual-perspective delta passes, hand-written ESP32-S3 PIE update kernels with exact wraparound semantics). Desktop stays bit-exact with the previous binary - strength gate over 200 games at 2+0.02 read 39-42-119 (-5.2 +/- 30.7). Design notes: docs/paired-fused-nnue.md in the repo.
• Fixed a long-bench bug (1 << 31 overflow made the bench quit after depth 1).
• Board gates on this firmware: 3-game board-vs-native clean, 737-round / 16-minute 2-thread stability session clean, boot-time kernel selftests passing.

Contents

• Dog-native - Linux aarch64 UCI engine (same target as v0.1; built from a clean checkout of 31be6d3). md5 123c6e15285b260f6d6dbebb86e78367.
• board-flash.zip - firmware + web assets for the XIAO ESP32-S3 Plus. esp32chesstest.bin md5 77bb62cc75ea50bf7c16845e826a3686.

Flash the board

unzip board-flash.zip -d board-flash && cd board-flash
python -m esptool --port /dev/ttyACM0 write_flash "@flash_args"

Then power-cycle, join the DOG-CHESS WiFi, open http://192.168.4.1. Console users: send uci before UCI commands.

Building from source instead: see the README (ESP-IDF v5.3 via tools/setup_esp_idf.sh; verified by clean-clone build).

Prebuilt binaries - Tier-1 + Phase B state

Prebuilt state of the repo at commit 75e6d10 (Tier-1 harness + C2/C5, Phase B: razoring + check extension + qs SEE pruning).

• Dog-native: desktop build (Linux x86_64, gcc 14+, RelWithDebInfo + LTO), md5 1773e3c807d0752a40da2ae78ea82924, bench ~340k nps.
• board-flash.zip: complete ESP32-S3 flash bundle (bootloader, partition table, ota data, app firmware, spiffs) + flash_args. Flash with: python -m esptool --port /dev/ttyACM0 write_flash "@flash_args" (unzip into the board-flash dir first).