Modifications for v2.1.0

[stefanunrein]

New Features

• Added axi4lite_VersionRegister module and necessary files:
  • Entity axi4lite_GitVersionRegister
  • Package mem_GitVersionRegister
  • Synthesis pre-TCL script tools/git/preSynth_GitVersionRegister_Vivado.tcl
  • Entity xil_DNAPort
• Use sync_Bits for CDC in fifo_ic_got (code reruse and apply constraints automatically).
• Added empty/fill-level output for fifo_shift
• Add chunk-enable feature for comm_crc
• Support for fraction of one for type T_FRACTIONAL
• Entity list_expire
• Entity misc_Sequencer
• Entity misc_StrobeGenerator
• Entity misc_StrobeLimiter
• Entity misc_StrobeStretcher
• Entity mac_TX_Type_Prepender

Changes

• Check if Init value fits in downcounter; changed Init value's type a natural.
• Updated my_config template with GENERIC as device example

Bug Fixes

• bus_Arbiter: Throw failure when unimplemented lottery strategy is selected.
• Added missing VHDL sources to *.pro files for analyzing in simulators:
  • syntax check
  • instantiation check
• arith_scaler: Initialize arrays with '0' instead of '-' for better/easier simulation
• remote_terminal_control: Fix package name

Tests

• Run simulations additionally with GHDL mcode backend and NVC for better simulation coverage.

Clean-Up

• Remove all *.files, since they are outdated and the compile order is now defined by the *.pro files usable with OSVVM-Scripting.
• Remove old and unused VHDL files
  • sim/ obsoleted by OSVVM
  • Xilinx ISE related files

[Paebbels]

first part