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[WirelengthAnalyzer] Add support for IBUFDS_GTE4 cells #60

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Merged
merged 1 commit into from
Jan 8, 2024
Merged

[WirelengthAnalyzer] Add support for IBUFDS_GTE4 cells #60

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2 changes: 1 addition & 1 deletion docs/score.md
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Original file line number Diff line number Diff line change
Expand Up @@ -119,7 +119,7 @@ BEL input and output pins for each type of PhysCell.
|`LUT1`, `LUT2`, `LUT3`, `LUT4`, `LUT5`, `LUT6` | (all) <- (all) | Look Up Table |
|`CARRY8` | [see table CARRY8](#carry8-connectivity) | Fast Carry Logic |
|`MUXF7`, `MUXF8`, `MUXF9` | (all) <- (all) | Intrasite Mux |
|`IBUFCTRL`, `INBUF`, `OBUFT`, `DIFFINBUF` | (all) <- (all) | I/O Buffer |
|`IBUFCTRL`, `INBUF`, `OBUFT`, `DIFFINBUF`, `IBUFDS_GTE4` | (all) <- (all) | I/O Buffer |
|`DSP_A_B_DATA`, `DSP_C_DATA`, `DSP_M_DATA`,<br>`DSP_PREADD_DATA`, `DSP_OUTPUT`, `DSP_ALU` | (none) <- (none) [see note](#dsp-cell-connectivity) | DSP Logic |
|`DSP_MULTIPLIER`, `DSP_PREADD` | (all) <- (all) [see note](#dsp-cell-connectivity) | DSP Logic |
|`PCIE40E4` | (none) <- (none) | PCIe Hard Macro |
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1 change: 1 addition & 0 deletions wirelength_analyzer/xcvup_device_data.py
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Expand Up @@ -82,6 +82,7 @@ def __contains__(self, item):
'INBUF': self.all_to_all,
'OBUFT': self.all_to_all,
'DIFFINBUF': self.all_to_all,
'IBUFDS_GTE4': self.all_to_all,

# The following cell types are BELs that make up a DSP macro.
# Such DSPs contains a number of optional pipelining registers,
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