Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Test sram #5

Closed
danielitzahi opened this issue Aug 31, 2023 · 6 comments
Closed

Test sram #5

danielitzahi opened this issue Aug 31, 2023 · 6 comments

Comments

@danielitzahi
Copy link

Hi dan
in the cputest
Do You test full sram (0-ffff) ?
Best regard
Tzahi

@ZipCPU
Copy link
Owner

ZipCPU commented Aug 31, 2023

The design is built for 128kB of SRAM.

See here.

Dan

@ZipCPU ZipCPU closed this as completed Aug 31, 2023
@danielitzahi
Copy link
Author

Hi dan
I understend this
But on the cputest.c
On runing log i did not see any loop test
On the ext sram
Tzahi

@ZipCPU
Copy link
Owner

ZipCPU commented Aug 31, 2023

That's because the CPU test is a test of the CPU--somewhat independent of the RAM. (It needs RAM to operate, but doesn't specifically test the RAM.) If you want to test memory, you'll need to look for a memory test. Not all of my projects include the memory test.

Dan

@danielitzahi
Copy link
Author

hi dan
i appreciate your attention (:
i try to run your design on different board from icoboard but sram,fpga same, flash smallest 16mbit the cputest pass
flashid test fail all zero
the spi signal that from ice40 way to flash look strange
Whan i make bit reload to ice40
The spi > flash look good
Tzahi

@ZipCPU
Copy link
Owner

ZipCPU commented Sep 1, 2023

So ... it sounds like you need to debug the SPI interaction, no?

That's what the spixscope.txt configuration, and spixscope.cpp files are for: internal logic analyzers to look at what's going on over SPI. Perhaps you wish to run the flashid, and trigger the scope to see what's going on within? You might also wish to run the basic commands within the flashid program from wbregs. That's usually my progression: get the flashid first via wbregs, then get flashid working, then get the full flash driver working. A common problem with flashid, by the way, is that the number of clocksbetween the device returning the flash ID and the flash controller tend to change from one FPGA and memory chip to the next.

As for the memory, if I recall correctly there was an issue with the ICO board design which meant that either a PLL could be used or an IO could be used. (It might've even been the MSB address bit on the SRAM.) This is why the ICOZip design doesn't use any PLLs to get the clock to the right frequency. Doing so would've broken something else. (This is from memory, though, it's been quite a while since I worked with this particular design.)

Dan

@danielitzahi
Copy link
Author

20230921_103408

Hi dan
How are you?
I'm very happy about your site zipcpu
I had success with the flash controller :) It works with hello sample I used spixscop to debug
My next question is whether after writing the software into the flash why after cpu reset or fpga reset (button) hello sample not running on boot. best regards
Tzahi

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

No branches or pull requests

2 participants