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Test sram #5
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The design is built for 128kB of SRAM. See here. Dan |
Hi dan |
That's because the CPU test is a test of the CPU--somewhat independent of the RAM. (It needs RAM to operate, but doesn't specifically test the RAM.) If you want to test memory, you'll need to look for a memory test. Not all of my projects include the memory test. Dan |
hi dan |
So ... it sounds like you need to debug the SPI interaction, no? That's what the spixscope.txt configuration, and spixscope.cpp files are for: internal logic analyzers to look at what's going on over SPI. Perhaps you wish to run the flashid, and trigger the scope to see what's going on within? You might also wish to run the basic commands within the flashid program from wbregs. That's usually my progression: get the flashid first via wbregs, then get flashid working, then get the full flash driver working. A common problem with flashid, by the way, is that the number of clocksbetween the device returning the flash ID and the flash controller tend to change from one FPGA and memory chip to the next. As for the memory, if I recall correctly there was an issue with the ICO board design which meant that either a PLL could be used or an IO could be used. (It might've even been the MSB address bit on the SRAM.) This is why the ICOZip design doesn't use any PLLs to get the clock to the right frequency. Doing so would've broken something else. (This is from memory, though, it's been quite a while since I worked with this particular design.) Dan |
Hi dan |
Hi dan
in the cputest
Do You test full sram (0-ffff) ?
Best regard
Tzahi
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