Opt_Guide

Software Code Prefetch

SW prefetch instructions for code — PREFETCHIT1 and PREFETCHIT0 — can improve the performance of large code footprint workloads by prefetching code into the core ahead of time.

The support is for RIP-relative memory address and in 64-bit mode only. RIP-relative lets the processor fetch the specified code line address early during the fetch pipeline. This choice avoids the need for software to hoist prefetch too far ahead of the miss site; hence, fewer paths leading to the miss site need to be covered.

Compared to PFEFETCHT2, the new instructions do not pollute the data TLBs with instruction lines and fetch the line in a Shared coherency state.

Prefetch Insertions

• Prefetch i-cache (IC) misses that are the target of BTB-miss (also known as Unknown Branch).
  • Hard icache-misses are targets of jumps.
  • BPU run-ahead can fetch IC-miss in the shadow of known branches (no BAClear).
  • Thus, the most critical IC-misses: jump (BTB-miss) -> target (IC-miss).
• Use large pages.
  • Let the prefetch hit in iTLB.
• Other guidelines.
  • Valid address[5:0] bits.
  • Support a single prefetch per 32B line unless two prefetches are spaced by eight instructions.
  • Lines to be prefetched are fully packed (no 0000H).
  • Do not use 0F 18 /4-7H as a NOP. Intel’s SDM recommends 0F 1F 80 00 00 00 00H for a 7-byte NOP.

Profiling for Code Prefetch

The following PMU capabilities may be used to identify prefetch candidates and facilitate prefetch insertion for the aforementioned PREFETCHIT1 instruction.

PMU Events

FRONTEND_RETIRED.L2_MISS
FRONTEND_RETIRED.UNKNOWN_BRANCH
FRONTEND_RETIRED.LATENCY_GE_64/128
FRONTEND_RETIRED.LATE_SWPF

• Timed PEBS: New Retire Latency field for all precise samples.

Refer to https://perfmon-events.intel.com/ for programming details of performance monitoring events.

Performance Metrics

Background

Starting with Arch PerfMon Version 5 (Ice Lake), the Intel P-Core PMU provides built-in support for the top levels metrics of the Top-down Microarchitecture Analysis (TMA) method. These metrics are always available to cross-validate telemetries, freeing general purpose counters to count other events in high counter utilization scenarios.

A new MSR called PERF_METRICS reports the metrics directly. This register exposes four (or eight) TMA Level 1 (and Level 2) metrics. Each metric field is an 8-bit integer fraction of 255.

Backend Bound	Frontend Bound	Bad Speculation	Retiring
Bits 31 .. 24	23 ..16	15 .. 8	7 .. 0

Memory Bound	Fetch Latency	Branch Mispredicts	Heavy Operations
Bits 63 .. 56	55 ..48	47 .. 40	39 .. 32

Software can check the availability of the PERF_METRICS feature using IA32_PERF_CAPABILITIES.PERF_METRICS_AVAILABLE. For details, refer to the Performance Monitoring chapter of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3; name the sub-section for your processor under 21.3 Performance Monitoring (Intel® Core™ Processors and Intel® Xeon® Processors).

Sampling with PERF_METRICS

Fixed counter 3 and PERF_METRICS can be used in Event-Based-Counting (EBC) mode. This needs to be carefully done per the sampling period (in Linux perf terms). Sampling period is also called Sample-After-Value (SAV) by Intel tools.

Example pseudo code:

Assume Fixed counter 3 has just overflowed (IA32_PERF_GLOBAL_STATUS[bit 35] is set)

1. Globally stop all counters
2. WRMSR +SAV (positive period value) to Fixed counter 3
3. RDPMC for PERF_METRICS and log them at the Instruction Pointer of this sample
4. WRMSR -SAV (negative period value) to Fixed counter 3
5. WRMSR of zero to (clear) PERF_METRICS. This step may be lumped with step 3 if IA32_PERF_CAPABILITIES.RDPMC_METRICS_CLEAR is set
6. Globally resume all counters
7. ...
8. IRET