Project of the Networks and Technologies for Telecommunications course of the Computer Science and Networking Master's Degree @ University of Pisa. The aim of the project is to deal with the implementation of Adders, Subtractors and Multipliers in Verilog HDL. The tests have been conducted on both the Quartus University Program Waveform Simulator and on the DE2-115 series FPGA board.
Note: Every solution contains an “interface” to the FPGA board to ease pin assignments. Moreover, every solution also contains a module that given a 4 bits input (interpreted as an unsigned integer) it outputs the value on a 7-segment screen like the ones on the board.
| Part number | Description |
|---|---|
| 1 | The implementation of an accumulator module that takes as input an 8 bit 2’s-complement number. The sequential circuit has been modeled as a finite state machine with two states: in the go state the input value is read (and put in the register A) and the sum is executed (content of register S is updated); in the case in which an overflow occurs in the sum the finish state is reached and the computation terminates. |
| 2 | An extension of the previous part. The circuit now provides both addition and subtraction and the type of operation to be performed on the input value depends on the value of the new input add_sub. |
| 3 | The implementation of an array multiplier circuit that performs the product between the two 4 bits input values A and B as a sum of intermediate values computed as the AND of A and the appropriate bit of B. The sums are generated by full adder binary modules connected in a regular structure (a grid). An alternative implementation is also provided that take advantage of the Verilog's generate construct. In this case the summands intermediate terms are generated as 8 bits values and added at the end. |
| 4 | An extension of the previous part. The requested inputs are two 8 bits numbers, so the output is a 16 bits number in this case. The intermediate rows are now implemented as 8 bits adders, each one composed of a sequence of 8 binary full adders. The multiplier module implemented in this way is then inserted in a sequential circuit where both the inputs and the output values are put in enabled registers. Also this time an alternative implementation using Verilog’s generate construct is provided; in particular, the 8 bits adder is created using a generated sequence of 8 binary full adders. |
| 5 | A variation of the part 4 where the 8 bits adder is organized as a tree of sums of already-shifted and padded addends: sums that are on the same level of the tree can be conducted in parallel, so there’s an increase in computation speed. In the previous implementation of an 8 bits adder (a linear sequence of full adders) each one of them must wait its predecessor to finish before it can use the relevant carry bit. |