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Lifts x86_64 1-operand widening mul / imul (8/16/32/64-bit, collapsing high/low u128 / i128 splits into clean wide shifts/casts when both halves are consumed and preserving upper register bits on 8/16-bit subword writes).
Lifts 1-operand div / idiv (8/16/32/64-bit) with zero-extended low halves ((u128)(u64)), SSA-proven cbw / cwd / cdq / cqo sign-extension folding on idiv, and accumulator sign-extension instructions (cbw, cwde, cdqe, cwd, cdq, cqo).
Lifts multi-precision adc / sbb across 8/16/32/64-bit operands with width-aware Flags::Add / Flags::Sub carry/borrow propagation, pre-mutation cf_<ip> / lhs_<ip> / rhs_<ip> snapshotting across flag lifetimes, and CF preservation across inc / dec / not / bswap (#26, #27).