GitHub - algorhtym/mips-pipelined-processor: A digital design project for a MIPS Reduced Instruction Set Computer (RISC) pipelined processor design that has a 5 stage basic pipeline and supports 32-bit MIPS instructions with an 8-bit wide datapath, on a 256x32 ROM and 256x8 RAM, implemented through structural VHDL

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A digital design project for a MIPS Reduced Instruction Set Computer (RISC) pipelined processor design that has a 5 stage basic pipeline and supports 32-bit MIPS instructions with an 8-bit wide datapath, on a 256x32 ROM and 256x8 RAM, implemented through structural VHDL

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Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
testedmiffiles		testedmiffiles
ALU_8bit.vhd		ALU_8bit.vhd
ALU_control.vhd		ALU_control.vhd
EX_MEM_Buffer.vhd		EX_MEM_Buffer.vhd
ID_EX_Buffer.vhd		ID_EX_Buffer.vhd
IF_ID_Buffer.vhd		IF_ID_Buffer.vhd
MEM_WB_Buffer.vhd		MEM_WB_Buffer.vhd
adder_8bit.vhd		adder_8bit.vhd
and_6.vhd		and_6.vhd
comparator_4bit.vhd		comparator_4bit.vhd
comparator_5bit.vhd		comparator_5bit.vhd
comparator_8bit.vhd		comparator_8bit.vhd
d_Latch.vhd		d_Latch.vhd
decoder_3x8.vhd		decoder_3x8.vhd
dflipflop.vhd		dflipflop.vhd
fa_1bit.vhd		fa_1bit.vhd
forwardingUnit.vhd		forwardingUnit.vhd
hazardDetectUnit.vhd		hazardDetectUnit.vhd
instr_mem.mif		instr_mem.mif
instr_mem.vhd		instr_mem.vhd
instr_mem2.mif		instr_mem2.mif
instr_mem_inst.vhd		instr_mem_inst.vhd
instructionOutRegister.vhd		instructionOutRegister.vhd
main_mem.mif		main_mem.mif
main_mem.vhd		main_mem.vhd
main_mem_inst.vhd		main_mem_inst.vhd
mux_1bit_8x1.vhd		mux_1bit_8x1.vhd
mux_5bit_2x1.vhd		mux_5bit_2x1.vhd
mux_8bit_2x1.vhd		mux_8bit_2x1.vhd
mux_8bit_4x1.vhd		mux_8bit_4x1.vhd
mux_8bit_8x1.vhd		mux_8bit_8x1.vhd
onebitcomparator.vhd		onebitcomparator.vhd
overflowDetector.vhd		overflowDetector.vhd
pipelinedProc.vhd		pipelinedProc.vhd
pipelinedProc_test.vwf		pipelinedProc_test.vwf
reg_32bit.vhd		reg_32bit.vhd
reg_5bit.vhd		reg_5bit.vhd
reg_8bit.vhd		reg_8bit.vhd
register_file_8x8.vhd		register_file_8x8.vhd
sign_truncate_16to8.vhd		sign_truncate_16to8.vhd
ssp_control.vhd		ssp_control.vhd
xor_2.vhd		xor_2.vhd