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platform.add_clock_constraint does not work for instances with lattice diamond for machxo2 #546

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anuejn opened this issue Nov 19, 2020 · 16 comments

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@anuejn
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anuejn commented Nov 19, 2020

Similiar to #373 platform.add_clock_constraint does not work for instances in lattice diamond.
However, the same fix does not seem to be applicable. Do you have any ideas what is going wrong?

repro:

from nmigen import *
from nmigen.build import *
from nmigen_boards.tinyfpga_ax2 import *

class Test(Elaboratable):
    def elaborate(self, plat):
        m = Module()
        clk = Signal()
        m.submodules.inst = Instance("JTAGF", o_JTCK=clk)

        m.domains += ClockDomain("sync")
        m.d.comb += ClockSignal().eq(clk)

        plat.add_clock_constraint(clk, 2e6)

        plat.add_resources([Resource("gpio", 0, Pins("1", conn=("gpio", 0), dir="o"), Attrs(IOSTANDARD="LVCMOS33"))])
        gpio0 = plat.request("gpio", 0)
        m.d.sync += gpio0.eq(~gpio0)

        return m

TinyFPGAAX2Platform().build(Test())
@whitequark
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What is the error you're getting?

@anuejn
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anuejn commented Nov 19, 2020

in build/top_impl/top_impl_cck.rpt:

create_clock -name clk -period 500.0 [get_nets {clk$1}]
	@E::"/home/anuejn/tmp/repro/build/top.sdc":1:0:1:0|Source for clock clk not found in netlist.

@anuejn
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anuejn commented Nov 19, 2020

build.zip

@whitequark
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It probably doesn't like the $. That doesn't happen for ports because ports are named first. Try Instance("JTAGF", o_JTCK=ClockSignal()).

@anuejn
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anuejn commented Nov 19, 2020

How can I constrain it then?

@whitequark
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whitequark commented Nov 19, 2020

cd_sync = ClockDomain()
platform.add_clock_constraint(cd_sync.clk, freq)

@anuejn
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anuejn commented Nov 19, 2020

Thanks that works. Somehow it doesnt work for my non minimized use case :(. I will try to find another (less minimized) example

@anuejn
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anuejn commented Nov 19, 2020

This also doesnt work, probably due to hierarchy:

from nmigen import *
from nmigen.build import *
from nmigen_boards.tinyfpga_ax2 import *

class Test(Elaboratable):
    def elaborate(self, plat):
        m = Module()

        m.submodules.jtag = JTAG()

        return m

class JTAG(Elaboratable):
    def elaborate(self, plat):
        m = Module()

        cd_sync = ClockDomain("sync")
        m.domains += cd_sync
        plat.add_clock_constraint(cd_sync.clk, 2e6)


        plat.add_resources([Resource("gpio", 0, Pins("1", conn=("gpio", 0), dir="o"), Attrs(IOSTANDARD="LVCMOS33"))])
        gpio0 = plat.request("gpio", 0)
        m.d.sync += gpio0.eq(~gpio0)


        m.submodules.inst = Instance("JTAGF", o_JTCK=cd_sync.clk)

        return m

TinyFPGAAX2Platform().build(Test())

the error is


create_clock -name clk -period 500.0 [get_nets jtag/clk]
	@E::"/home/anuejn/tmp/repro/build/top.sdc":1:0:1:0|Source for clock clk not found in netlist.

build.zip

@whitequark
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The second one is a very serious issue, and one we can already fix (the $ problem is more thorny). You should research how to specify hierarchy for Diamond.

@anuejn
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anuejn commented Nov 19, 2020

Sadly I am not at all good with diamond but I will try my best.
Maybe @cr1901 can help here too?

@whitequark
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I am not good with it either. I'm just persistent enough that eventually I fix this stuff when it becomes my responsibility.

@anuejn
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anuejn commented Nov 19, 2020

Okay according to some microsemi guide to synplify pro you have to use "." as a hierarchy seperator jUsT iN SdC FiLeS.
And it works :).

Should i file a PR that fixes that?

@whitequark
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Yep.

@whitequark
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Or maybe use set_hierarchy_separator {/} ?

@anuejn
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anuejn commented Nov 19, 2020

The first example really works when we escape $ with a \ in front of it as @cr1901 suggested :)

@anuejn
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anuejn commented Nov 19, 2020

Or maybe use set_hierarchy_separator {/} ?

Tested. Works

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