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AndreiGrozavAndreiGrozav
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axi_ad9371: Updates for ad_dds phase acc wrapper
1 parent 42abe0c commit 25dbca7

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6 files changed

+48
-80
lines changed

6 files changed

+48
-80
lines changed

‎library/axi_ad9371/Makefile

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,9 @@ LIBRARY_NAME := axi_ad9371
88
GENERIC_DEPS += ../common/ad_datafmt.v
99
GENERIC_DEPS += ../common/ad_dds.v
1010
GENERIC_DEPS += ../common/ad_dds_1.v
11+
GENERIC_DEPS += ../common/ad_dds_cordic_pipe.v
1112
GENERIC_DEPS += ../common/ad_dds_sine.v
13+
GENERIC_DEPS += ../common/ad_dds_sine_cordic.v
1214
GENERIC_DEPS += ../common/ad_iqcor.v
1315
GENERIC_DEPS += ../common/ad_rst.v
1416
GENERIC_DEPS += ../common/ad_xcvr_rx_if.v
@@ -28,6 +30,7 @@ GENERIC_DEPS += axi_ad9371_rx_os.v
2830
GENERIC_DEPS += axi_ad9371_tx.v
2931
GENERIC_DEPS += axi_ad9371_tx_channel.v
3032

33+
XILINX_DEPS += ../common/ad_dds_2.v
3134
XILINX_DEPS += ../xilinx/common/ad_dcfilter.v
3235
XILINX_DEPS += ../xilinx/common/ad_mul.v
3336
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc

‎library/axi_ad9371/axi_ad9371.v

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,7 @@ module axi_ad9371 #(
4040
parameter ID = 0,
4141
parameter DAC_DDS_TYPE = 1,
4242
parameter DAC_DDS_CORDIC_DW = 16,
43+
parameter DAC_DDS_CORDIC_PHASE_DW = 16,
4344
parameter DAC_DATAPATH_DISABLE = 0,
4445
parameter ADC_DATAPATH_DISABLE = 0) (
4546

@@ -263,8 +264,9 @@ module axi_ad9371 #(
263264

264265
axi_ad9371_tx #(
265266
.ID (ID),
266-
.DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
267-
.DDS_TYPE (DAC_DDS_TYPE),
267+
.DAC_DDS_TYPE (DAC_DDS_TYPE),
268+
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
269+
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
268270
.DATAPATH_DISABLE (DAC_DATAPATH_DISABLE))
269271
i_tx (
270272
.dac_rst (dac_rst),

‎library/axi_ad9371/axi_ad9371_hw.tcl

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@ add_fileset_file ad_mul.v VERILOG PATH $ad_hdl_dir/library/alt
1919
add_fileset_file ad_dds_cordic_pipe.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_cordic_pipe.v
2020
add_fileset_file ad_dds_sine_cordic.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine_cordic.v
2121
add_fileset_file ad_dds_sine.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v
22+
add_fileset_file ad_dds_2.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_2.v
2223
add_fileset_file ad_dds_1.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_1.v
2324
add_fileset_file ad_dds.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds.v
2425
add_fileset_file ad_datafmt.v VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v

‎library/axi_ad9371/axi_ad9371_ip.tcl

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@ adi_ip_files axi_ad9371 [list \
1515
"$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \
1616
"$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \
1717
"$ad_hdl_dir/library/common/ad_dds_sine.v" \
18+
"$ad_hdl_dir/library/common/ad_dds_2.v" \
1819
"$ad_hdl_dir/library/common/ad_dds_1.v" \
1920
"$ad_hdl_dir/library/common/ad_dds.v" \
2021
"$ad_hdl_dir/library/common/ad_datafmt.v" \

‎library/axi_ad9371/axi_ad9371_tx.v

Lines changed: 15 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -38,8 +38,9 @@
3838
module axi_ad9371_tx #(
3939

4040
parameter ID = 0,
41-
parameter DDS_TYPE = 1,
42-
parameter DDS_CORDIC_DW = 16,
41+
parameter DAC_DDS_TYPE = 1,
42+
parameter DAC_DDS_CORDIC_DW = 16,
43+
parameter DAC_DDS_CORDIC_PHASE_DW = 16,
4344
parameter DATAPATH_DISABLE = 0) (
4445

4546
// dac interface
@@ -131,8 +132,9 @@ module axi_ad9371_tx #(
131132
axi_ad9371_tx_channel #(
132133
.CHANNEL_ID (0),
133134
.Q_OR_I_N (0),
134-
.DDS_CORDIC_DW (DDS_CORDIC_DW),
135-
.DDS_TYPE (DDS_TYPE),
135+
.DAC_DDS_TYPE (DAC_DDS_TYPE),
136+
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
137+
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
136138
.DATAPATH_DISABLE (DATAPATH_DISABLE))
137139
i_tx_channel_0 (
138140
.dac_clk (dac_clk),
@@ -162,8 +164,9 @@ module axi_ad9371_tx #(
162164
axi_ad9371_tx_channel #(
163165
.CHANNEL_ID (1),
164166
.Q_OR_I_N (1),
165-
.DDS_CORDIC_DW (DDS_CORDIC_DW),
166-
.DDS_TYPE (DDS_TYPE),
167+
.DAC_DDS_TYPE (DAC_DDS_TYPE),
168+
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
169+
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
167170
.DATAPATH_DISABLE (DATAPATH_DISABLE))
168171
i_tx_channel_1 (
169172
.dac_clk (dac_clk),
@@ -193,8 +196,9 @@ module axi_ad9371_tx #(
193196
axi_ad9371_tx_channel #(
194197
.CHANNEL_ID (2),
195198
.Q_OR_I_N (0),
196-
.DDS_CORDIC_DW (DDS_CORDIC_DW),
197-
.DDS_TYPE (DDS_TYPE),
199+
.DAC_DDS_TYPE (DAC_DDS_TYPE),
200+
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
201+
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
198202
.DATAPATH_DISABLE (DATAPATH_DISABLE))
199203
i_tx_channel_2 (
200204
.dac_clk (dac_clk),
@@ -224,8 +228,9 @@ module axi_ad9371_tx #(
224228
axi_ad9371_tx_channel #(
225229
.CHANNEL_ID (3),
226230
.Q_OR_I_N (1),
227-
.DDS_CORDIC_DW (DDS_CORDIC_DW),
228-
.DDS_TYPE (DDS_TYPE),
231+
.DAC_DDS_TYPE (DAC_DDS_TYPE),
232+
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
233+
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
229234
.DATAPATH_DISABLE (DATAPATH_DISABLE))
230235
i_tx_channel_3 (
231236
.dac_clk (dac_clk),

‎library/axi_ad9371/axi_ad9371_tx_channel.v

Lines changed: 24 additions & 68 deletions
Original file line numberDiff line numberDiff line change
@@ -39,8 +39,9 @@ module axi_ad9371_tx_channel #(
3939

4040
parameter CHANNEL_ID = 32'h0,
4141
parameter Q_OR_I_N = 0,
42-
parameter DDS_TYPE = 1,
43-
parameter DDS_CORDIC_DW = 16,
42+
parameter DAC_DDS_TYPE = 1,
43+
parameter DAC_DDS_CORDIC_DW = 16,
44+
parameter DAC_DDS_CORDIC_PHASE_DW = 16,
4445
parameter DATAPATH_DISABLE = 0) (
4546

4647
// dac interface
@@ -75,18 +76,10 @@ module axi_ad9371_tx_channel #(
7576
// internal registers
7677

7778
reg [31:0] dac_pat_data = 'd0;
78-
reg [15:0] dac_dds_phase_0_0 = 'd0;
79-
reg [15:0] dac_dds_phase_0_1 = 'd0;
80-
reg [15:0] dac_dds_phase_1_0 = 'd0;
81-
reg [15:0] dac_dds_phase_1_1 = 'd0;
82-
reg [15:0] dac_dds_incr_0 = 'd0;
83-
reg [15:0] dac_dds_incr_1 = 'd0;
84-
reg [31:0] dac_dds_data = 'd0;
8579

8680
// internal signals
8781

88-
wire [15:0] dac_dds_data_0_s;
89-
wire [15:0] dac_dds_data_1_s;
82+
wire [31:0] dac_dds_data_s;
9083
wire [15:0] dac_dds_scale_1_s;
9184
wire [15:0] dac_dds_init_1_s;
9285
wire [15:0] dac_dds_incr_1_s;
@@ -141,7 +134,7 @@ module axi_ad9371_tx_channel #(
141134
4'h3: dac_data_iq_out <= 32'd0;
142135
4'h2: dac_data_iq_out <= dac_data_in;
143136
4'h1: dac_data_iq_out <= dac_pat_data;
144-
default: dac_data_iq_out <= dac_dds_data;
137+
default: dac_data_iq_out <= dac_dds_data_s;
145138
endcase
146139
end
147140

@@ -153,64 +146,27 @@ module axi_ad9371_tx_channel #(
153146

154147
// dds
155148

156-
always @(posedge dac_clk) begin
157-
if (dac_data_sync == 1'b1) begin
158-
dac_dds_phase_0_0 <= dac_dds_init_1_s;
159-
dac_dds_phase_0_1 <= dac_dds_init_2_s;
160-
dac_dds_phase_1_0 <= dac_dds_phase_0_0 + dac_dds_incr_1_s;
161-
dac_dds_phase_1_1 <= dac_dds_phase_0_1 + dac_dds_incr_2_s;
162-
dac_dds_incr_0 <= {dac_dds_incr_1_s[14:0], 1'd0};
163-
dac_dds_incr_1 <= {dac_dds_incr_2_s[14:0], 1'd0};
164-
dac_dds_data <= 32'd0;
165-
end else begin
166-
dac_dds_phase_0_0 <= dac_dds_phase_0_0 + dac_dds_incr_0;
167-
dac_dds_phase_0_1 <= dac_dds_phase_0_1 + dac_dds_incr_1;
168-
dac_dds_phase_1_0 <= dac_dds_phase_1_0 + dac_dds_incr_0;
169-
dac_dds_phase_1_1 <= dac_dds_phase_1_1 + dac_dds_incr_1;
170-
dac_dds_incr_0 <= dac_dds_incr_0;
171-
dac_dds_incr_1 <= dac_dds_incr_1;
172-
dac_dds_data <= {dac_dds_data_1_s, dac_dds_data_0_s};
173-
end
174-
end
175-
176-
// dds
177-
178-
generate
179-
if (DATAPATH_DISABLE == 1) begin
180-
181-
assign dac_dds_data_0_s = 16'd0;
182-
assign dac_dds_data_1_s = 16'd0;
183-
184-
end else begin
185-
186-
ad_dds #(
187-
.DISABLE (0),
188-
.DDS_TYPE (DDS_TYPE),
189-
.CORDIC_DW (DDS_CORDIC_DW))
190-
i_dds_0 (
191-
.clk (dac_clk),
192-
.dds_format (dac_dds_format),
193-
.dds_phase_0 (dac_dds_phase_0_0),
194-
.dds_scale_0 (dac_dds_scale_1_s),
195-
.dds_phase_1 (dac_dds_phase_0_1),
196-
.dds_scale_1 (dac_dds_scale_2_s),
197-
.dds_data (dac_dds_data_0_s));
198-
199149
ad_dds #(
200-
.DISABLE (0),
201-
.DDS_TYPE (DDS_TYPE),
202-
.CORDIC_DW (DDS_CORDIC_DW))
203-
i_dds_1 (
150+
.DISABLE (DATAPATH_DISABLE),
151+
.DDS_DW (16),
152+
.PHASE_DW (16),
153+
.DDS_TYPE (DAC_DDS_TYPE),
154+
.CORDIC_DW (DAC_DDS_CORDIC_DW),
155+
.CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
156+
.CLK_RATIO (2))
157+
i_dds (
204158
.clk (dac_clk),
205-
.dds_format (dac_dds_format),
206-
.dds_phase_0 (dac_dds_phase_1_0),
207-
.dds_scale_0 (dac_dds_scale_1_s),
208-
.dds_phase_1 (dac_dds_phase_1_1),
209-
.dds_scale_1 (dac_dds_scale_2_s),
210-
.dds_data (dac_dds_data_1_s));
159+
.dac_dds_format (dac_dds_format),
160+
.dac_data_sync (dac_data_sync),
161+
.dac_valid (1'b1),
162+
.tone_1_scale (dac_dds_scale_1_s),
163+
.tone_2_scale (dac_dds_scale_2_s),
164+
.tone_1_init_offset (dac_dds_init_1_s),
165+
.tone_2_init_offset (dac_dds_init_2_s),
166+
.tone_1_freq_word (dac_dds_incr_1_s),
167+
.tone_2_freq_word (dac_dds_incr_2_s),
168+
.dac_dds_data (dac_dds_data_s));
211169

212-
end
213-
endgenerate
214170

215171
// single channel processor
216172

@@ -254,7 +210,7 @@ module axi_ad9371_tx_channel #(
254210
.up_raddr (up_raddr),
255211
.up_rdata (up_rdata),
256212
.up_rack (up_rack));
257-
213+
258214
endmodule
259215

260216
// ***************************************************************************

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