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AndreiGrozavAndreiGrozav
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axi_ad9361: Updates for ad_dds phase acc wrapper
1 parent d27ed93 commit 42abe0c

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6 files changed

+58
-60
lines changed

6 files changed

+58
-60
lines changed

‎library/axi_ad9361/Makefile

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,10 @@ GENERIC_DEPS += ../common/ad_addsub.v
99
GENERIC_DEPS += ../common/ad_datafmt.v
1010
GENERIC_DEPS += ../common/ad_dds.v
1111
GENERIC_DEPS += ../common/ad_dds_1.v
12+
GENERIC_DEPS += ../common/ad_dds_2.v
13+
GENERIC_DEPS += ../common/ad_dds_cordic_pipe.v
1214
GENERIC_DEPS += ../common/ad_dds_sine.v
15+
GENERIC_DEPS += ../common/ad_dds_sine_cordic.v
1316
GENERIC_DEPS += ../common/ad_iqcor.v
1417
GENERIC_DEPS += ../common/ad_pnmon.v
1518
GENERIC_DEPS += ../common/ad_pps_receiver.v

‎library/axi_ad9361/axi_ad9361.v

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,8 @@ module axi_ad9361 #(
5757
parameter DAC_DATAPATH_DISABLE = 0,
5858
parameter DAC_DDS_DISABLE = 0,
5959
parameter DAC_DDS_TYPE = 1,
60-
parameter DAC_DDS_CORDIC_DW = 16,
60+
parameter DAC_DDS_CORDIC_DW = 14,
61+
parameter DAC_DDS_CORDIC_PHASE_DW = 13,
6162
parameter DAC_USERPORTS_DISABLE = 0,
6263
parameter DAC_IQCORRECTION_DISABLE = 0,
6364
parameter IO_DELAY_GROUP = "dev_if_delay_group") (
@@ -635,9 +636,10 @@ module axi_ad9361 #(
635636
.CMOS_OR_LVDS_N (CMOS_OR_LVDS_N),
636637
.PPS_RECEIVER_ENABLE (PPS_RECEIVER_ENABLE),
637638
.INIT_DELAY (DAC_INIT_DELAY),
638-
.DDS_DISABLE (DAC_DDS_DISABLE_INT),
639-
.DDS_TYPE (DAC_DDS_TYPE),
640-
.CORDIC_DW (DAC_DDS_CORDIC_DW),
639+
.DAC_DDS_DISABLE (DAC_DDS_DISABLE_INT),
640+
.DAC_DDS_TYPE (DAC_DDS_TYPE),
641+
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
642+
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
641643
.USERPORTS_DISABLE (DAC_USERPORTS_DISABLE_INT),
642644
.DELAYCNTRL_DISABLE (DAC_DELAYCNTRL_DISABLE_INT),
643645
.IQCORRECTION_DISABLE (DAC_IQCORRECTION_DISABLE_INT))

‎library/axi_ad9361/axi_ad9361_hw.tcl

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@ ad_ip_files axi_ad9361 [list\
1212
$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v \
1313
$ad_hdl_dir/library/common/ad_dds_sine_cordic.v \
1414
$ad_hdl_dir/library/common/ad_dds_sine.v \
15+
$ad_hdl_dir/library/common/ad_dds_2.v \
1516
$ad_hdl_dir/library/common/ad_dds_1.v \
1617
$ad_hdl_dir/library/common/ad_dds.v \
1718
$ad_hdl_dir/library/common/ad_datafmt.v \

‎library/axi_ad9361/axi_ad9361_ip.tcl

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@ adi_ip_files axi_ad9361 [list \
1515
"$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \
1616
"$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \
1717
"$ad_hdl_dir/library/common/ad_dds_sine.v" \
18+
"$ad_hdl_dir/library/common/ad_dds_2.v" \
1819
"$ad_hdl_dir/library/common/ad_dds_1.v" \
1920
"$ad_hdl_dir/library/common/ad_dds.v" \
2021
"$ad_hdl_dir/library/common/ad_datafmt.v" \

‎library/axi_ad9361/axi_ad9361_tx.v

Lines changed: 21 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -45,9 +45,10 @@ module axi_ad9361_tx #(
4545
parameter CMOS_OR_LVDS_N = 0,
4646
parameter PPS_RECEIVER_ENABLE = 0,
4747
parameter INIT_DELAY = 0,
48-
parameter DDS_DISABLE = 0,
49-
parameter DDS_TYPE = 1,
50-
parameter CORDIC_DW = 16,
48+
parameter DAC_DDS_DISABLE = 0,
49+
parameter DAC_DDS_TYPE = 1,
50+
parameter DAC_DDS_CORDIC_DW = 14,
51+
parameter DAC_DDS_CORDIC_PHASE_DW = 13,
5152
parameter USERPORTS_DISABLE = 0,
5253
parameter DELAYCNTRL_DISABLE = 0,
5354
parameter IQCORRECTION_DISABLE = 0) (
@@ -119,7 +120,7 @@ module axi_ad9361_tx #(
119120

120121
localparam CONFIG = (PPS_RECEIVER_ENABLE * 256) +
121122
(CMOS_OR_LVDS_N * 128) +
122-
(DDS_DISABLE * 64) +
123+
(DAC_DDS_DISABLE * 64) +
123124
(DELAYCNTRL_DISABLE * 32) +
124125
(MODE_1R1T * 16) +
125126
(USERPORTS_DISABLE * 8) +
@@ -215,9 +216,10 @@ module axi_ad9361_tx #(
215216
.CHANNEL_ID (0),
216217
.Q_OR_I_N (0),
217218
.DISABLE (0),
218-
.DDS_DISABLE (DDS_DISABLE),
219-
.DDS_TYPE (DDS_TYPE),
220-
.CORDIC_DW (CORDIC_DW),
219+
.DAC_DDS_DISABLE (DAC_DDS_DISABLE),
220+
.DAC_DDS_TYPE (DAC_DDS_TYPE),
221+
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
222+
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
221223
.USERPORTS_DISABLE (USERPORTS_DISABLE),
222224
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
223225
i_tx_channel_0 (
@@ -249,9 +251,10 @@ module axi_ad9361_tx #(
249251
.CHANNEL_ID (1),
250252
.Q_OR_I_N (1),
251253
.DISABLE (0),
252-
.DDS_DISABLE (DDS_DISABLE),
253-
.DDS_TYPE (DDS_TYPE),
254-
.CORDIC_DW (CORDIC_DW),
254+
.DAC_DDS_DISABLE (DAC_DDS_DISABLE),
255+
.DAC_DDS_TYPE (DAC_DDS_TYPE),
256+
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
257+
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
255258
.USERPORTS_DISABLE (USERPORTS_DISABLE),
256259
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
257260
i_tx_channel_1 (
@@ -283,9 +286,10 @@ module axi_ad9361_tx #(
283286
.CHANNEL_ID (2),
284287
.Q_OR_I_N (0),
285288
.DISABLE (MODE_1R1T),
286-
.DDS_DISABLE (DDS_DISABLE),
287-
.DDS_TYPE (DDS_TYPE),
288-
.CORDIC_DW (CORDIC_DW),
289+
.DAC_DDS_DISABLE (DAC_DDS_DISABLE),
290+
.DAC_DDS_TYPE (DAC_DDS_TYPE),
291+
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
292+
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
289293
.USERPORTS_DISABLE (USERPORTS_DISABLE),
290294
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
291295
i_tx_channel_2 (
@@ -317,9 +321,10 @@ module axi_ad9361_tx #(
317321
.CHANNEL_ID (3),
318322
.Q_OR_I_N (1),
319323
.DISABLE (MODE_1R1T),
320-
.DDS_DISABLE (DDS_DISABLE),
321-
.DDS_TYPE (DDS_TYPE),
322-
.CORDIC_DW (CORDIC_DW),
324+
.DAC_DDS_DISABLE (DAC_DDS_DISABLE),
325+
.DAC_DDS_TYPE (DAC_DDS_TYPE),
326+
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
327+
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
323328
.USERPORTS_DISABLE (USERPORTS_DISABLE),
324329
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
325330
i_tx_channel_3 (

‎library/axi_ad9361/axi_ad9361_tx_channel.v

Lines changed: 26 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -42,9 +42,10 @@ module axi_ad9361_tx_channel #(
4242
parameter Q_OR_I_N = 0,
4343
parameter CHANNEL_ID = 32'h0,
4444
parameter DISABLE = 0,
45-
parameter DDS_DISABLE = 0,
46-
parameter DDS_TYPE = 1,
47-
parameter CORDIC_DW = 16,
45+
parameter DAC_DDS_DISABLE = 0,
46+
parameter DAC_DDS_TYPE = 1,
47+
parameter DAC_DDS_CORDIC_DW = 14,
48+
parameter DAC_DDS_CORDIC_PHASE_DW = 13,
4849
parameter USERPORTS_DISABLE = 0,
4950
parameter IQCORRECTION_DISABLE = 0) (
5051

@@ -95,17 +96,12 @@ module axi_ad9361_tx_channel #(
9596
reg [23:0] dac_pn_seq = 'd0;
9697
reg [11:0] dac_pn_data = 'd0;
9798
reg [15:0] dac_pat_data = 'd0;
98-
reg [15:0] dac_dds_phase_0 = 'd0;
99-
reg [15:0] dac_dds_phase_1 = 'd0;
100-
reg [15:0] dac_dds_incr_0 = 'd0;
101-
reg [15:0] dac_dds_incr_1 = 'd0;
102-
reg [15:0] dac_dds_data = 'd0;
10399

104100
// internal signals
105101

106102
wire dac_iqcor_valid_s;
107103
wire [15:0] dac_iqcor_data_s;
108-
wire [15:0] dac_dds_data_s;
104+
wire [11:0] dac_dds_data_s;
109105
wire [15:0] dac_dds_scale_1_s;
110106
wire [15:0] dac_dds_init_1_s;
111107
wire [15:0] dac_dds_incr_1_s;
@@ -285,7 +281,7 @@ module axi_ad9361_tx_channel #(
285281
4'h3: dac_data_out_int <= 12'd0;
286282
4'h2: dac_data_out_int <= dma_data[15:4];
287283
4'h1: dac_data_out_int <= dac_pat_data[15:4];
288-
default: dac_data_out_int <= dac_dds_data[15:4];
284+
default: dac_data_out_int <= dac_dds_data_s;
289285
endcase
290286
end
291287

@@ -305,7 +301,7 @@ module axi_ad9361_tx_channel #(
305301
end
306302
end
307303
end
308-
304+
309305
// pattern
310306

311307
always @(posedge dac_clk) begin
@@ -320,36 +316,26 @@ module axi_ad9361_tx_channel #(
320316

321317
// dds
322318

323-
always @(posedge dac_clk) begin
324-
if (dac_data_sync == 1'b1) begin
325-
dac_dds_phase_0 <= dac_dds_init_1_s;
326-
dac_dds_phase_1 <= dac_dds_init_2_s;
327-
dac_dds_incr_0 <= dac_dds_incr_1_s;
328-
dac_dds_incr_1 <= dac_dds_incr_2_s;
329-
dac_dds_data <= 16'd0;
330-
end else if (dac_valid == 1'b1) begin
331-
dac_dds_phase_0 <= dac_dds_phase_0 + dac_dds_incr_0;
332-
dac_dds_phase_1 <= dac_dds_phase_1 + dac_dds_incr_1;
333-
dac_dds_incr_0 <= dac_dds_incr_0;
334-
dac_dds_incr_1 <= dac_dds_incr_1;
335-
dac_dds_data <= dac_dds_data_s;
336-
end
337-
end
338-
339-
// dds
340-
341319
ad_dds #(
342-
.DDS_TYPE (DDS_TYPE),
343-
.CORDIC_DW (CORDIC_DW),
344-
.DISABLE (DDS_DISABLE))
320+
.DISABLE (DAC_DDS_DISABLE),
321+
.DDS_DW (12),
322+
.PHASE_DW (16),
323+
.DDS_TYPE (DAC_DDS_TYPE),
324+
.CORDIC_DW (DAC_DDS_CORDIC_DW),
325+
.CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
326+
.CLK_RATIO (1))
345327
i_dds (
346328
.clk (dac_clk),
347-
.dds_format (dac_dds_format),
348-
.dds_phase_0 (dac_dds_phase_0),
349-
.dds_scale_0 (dac_dds_scale_1_s),
350-
.dds_phase_1 (dac_dds_phase_1),
351-
.dds_scale_1 (dac_dds_scale_2_s),
352-
.dds_data (dac_dds_data_s));
329+
.dac_dds_format (dac_dds_format),
330+
.dac_data_sync (dac_data_sync),
331+
.dac_valid (dac_valid),
332+
.tone_1_scale (dac_dds_scale_1_s),
333+
.tone_2_scale (dac_dds_scale_2_s),
334+
.tone_1_init_offset (dac_dds_init_1_s),
335+
.tone_2_init_offset (dac_dds_init_2_s),
336+
.tone_1_freq_word (dac_dds_incr_1_s),
337+
.tone_2_freq_word (dac_dds_incr_2_s),
338+
.dac_dds_data (dac_dds_data_s));
353339

354340
// single channel processor
355341

@@ -360,7 +346,7 @@ module axi_ad9361_tx_channel #(
360346
up_dac_channel #(
361347
.COMMON_ID (6'h11),
362348
.CHANNEL_ID (CHANNEL_ID),
363-
.DDS_DISABLE (DDS_DISABLE),
349+
.DDS_DISABLE (DAC_DDS_DISABLE),
364350
.USERPORTS_DISABLE (USERPORTS_DISABLE),
365351
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
366352
i_up_dac_channel (
@@ -403,7 +389,7 @@ module axi_ad9361_tx_channel #(
403389
.up_raddr (up_raddr),
404390
.up_rdata (up_rdata_s),
405391
.up_rack (up_rack_s));
406-
392+
407393
endmodule
408394

409395
// ***************************************************************************

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