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AndreiGrozavAndreiGrozav
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m2k: Remove dac last_sample_hold control
axi_dac_interpolate - Remove last sample hold control axi_ad9963 - Remove last sample hold control and set as default the last sample hold functionality plus code optimization changes.
1 parent 06201d5 commit 6998cc9

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7 files changed

+20
-69
lines changed

7 files changed

+20
-69
lines changed

‎library/axi_ad9963/axi_ad9963.v

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -107,8 +107,6 @@ module axi_ad9963 #(
107107
input dma_valid_q,
108108
input dac_dunf,
109109

110-
input hold_last_sample,
111-
112110
// axi interface
113111

114112
input s_axi_aclk,
@@ -169,8 +167,6 @@ module axi_ad9963 #(
169167
wire up_rack_tx_s;
170168
wire up_adc_ce;
171169
wire up_dac_ce;
172-
wire valid_out_q_s;
173-
wire valid_out_i_s;
174170

175171
// signal name changes
176172

@@ -208,10 +204,7 @@ module axi_ad9963 #(
208204
.adc_status (adc_status_s),
209205
.up_adc_ce(up_adc_ce),
210206
.dac_data (dac_data_s),
211-
.out_valid_q (valid_out_q_s),
212-
.out_valid_i (valid_out_i_s),
213207
.up_dac_ce(up_dac_ce),
214-
.tx_sample_hold (hold_last_sample),
215208
.up_clk (up_clk),
216209
.up_adc_dld (up_adc_dld_s),
217210
.up_adc_dwdata (up_adc_dwdata_s),
@@ -288,12 +281,10 @@ module axi_ad9963 #(
288281
.dac_valid_i (dac_valid_i),
289282
.dac_data_i (dac_data_i),
290283
.dma_valid_i (dma_valid_i),
291-
.out_valid_i (valid_out_i_s),
292284
.dac_enable_q (dac_enable_q),
293285
.dac_valid_q (dac_valid_q),
294286
.dac_data_q (dac_data_q),
295287
.dma_valid_q (dma_valid_q),
296-
.out_valid_q (valid_out_q_s),
297288
.dac_dunf(dac_dunf),
298289
.up_dac_ce(up_dac_ce),
299290
.up_rstn (up_rstn),

‎library/axi_ad9963/axi_ad9963_if.v

Lines changed: 4 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -73,11 +73,8 @@ module axi_ad9963_if #(
7373

7474
// transmit data path interface
7575

76-
input out_valid_q,
77-
input out_valid_i,
7876
input [23:0] dac_data,
7977
input up_dac_ce,
80-
input tx_sample_hold,
8178

8279
// delay interface
8380

@@ -93,16 +90,15 @@ module axi_ad9963_if #(
9390
// internal registers
9491

9592
reg [11:0] rx_data_p = 0;
96-
reg [11:0] tx_data_p = 'd0;
97-
reg [11:0] tx_data_n = 'd0;
98-
reg [23:0] constant_sample = 'd0;
9993

10094
// internal signals
10195

10296
wire [11:0] rx_data_p_s;
10397
wire [11:0] rx_data_n_s;
10498
wire rx_iq_p_s;
10599
wire rx_iq_n_s;
100+
wire [11:0] tx_data_p;
101+
wire [11:0] tx_data_n;
106102

107103
wire div_clk;
108104

@@ -119,26 +115,8 @@ module axi_ad9963_if #(
119115
end
120116
end
121117

122-
always @(posedge dac_clk) begin
123-
if (dac_rst == 1'b1) begin
124-
tx_data_p <= 24'd0;
125-
tx_data_n <= 24'd0;
126-
constant_sample <= 24'd0;
127-
end else begin
128-
if(out_valid_i == 1'b1) begin
129-
tx_data_p <= dac_data[11: 0];
130-
constant_sample[11: 0] <= tx_sample_hold ? dac_data[11: 0] : 12'd0;
131-
end else begin
132-
tx_data_p <= constant_sample[11:0] ;
133-
end
134-
if(out_valid_q == 1'b1) begin
135-
tx_data_n <= dac_data[23:12];
136-
constant_sample[23:12] <= tx_sample_hold ? dac_data[23:12] : 12'd0;
137-
end else begin
138-
tx_data_n <= constant_sample[23:12];
139-
end
140-
end
141-
end
118+
assign tx_data_p = dac_data[11: 0];
119+
assign tx_data_n = dac_data[23:12];
142120

143121
always @(posedge adc_clk) begin
144122
if (adc_rst == 1'b1) begin

‎library/axi_ad9963/axi_ad9963_tx.v

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -68,12 +68,10 @@ module axi_ad9963_tx #(
6868
output reg dac_valid_i,
6969
input [15:0] dac_data_i,
7070
input dma_valid_i,
71-
output out_valid_i,
7271
output dac_enable_q,
7372
output reg dac_valid_q,
7473
input [15:0] dac_data_q,
7574
input dma_valid_q,
76-
output out_valid_q,
7775
input dac_dunf,
7876

7977
output up_dac_ce,
@@ -147,7 +145,6 @@ module axi_ad9963_tx #(
147145
.dac_data_sync (dac_data_sync_s),
148146
.dac_dds_format (dac_dds_format_s),
149147
.dma_valid (dma_valid_i),
150-
.out_data_valid (out_valid_i),
151148
.up_rstn (up_rstn),
152149
.up_clk (up_clk),
153150
.up_wreq (up_wreq),
@@ -181,7 +178,6 @@ module axi_ad9963_tx #(
181178
.dac_data_sync (dac_data_sync_s),
182179
.dac_dds_format (dac_dds_format_s),
183180
.dma_valid (dma_valid_q),
184-
.out_data_valid (out_valid_q),
185181
.up_rstn (up_rstn),
186182
.up_clk (up_clk),
187183
.up_wreq (up_wreq),

‎library/axi_ad9963/axi_ad9963_tx_channel.v

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -58,7 +58,6 @@ module axi_ad9963_tx_channel #(
5858
output reg [11:0] dac_data_out,
5959
input [11:0] dac_data_in,
6060
input dma_valid,
61-
output out_data_valid,
6261

6362
// processor interface
6463

@@ -113,8 +112,6 @@ module axi_ad9963_tx_channel #(
113112
wire [15:0] dac_iqcor_coeff_1_s;
114113
wire [15:0] dac_iqcor_coeff_2_s;
115114

116-
assign out_data_valid = dac_iqcor_valid_s;
117-
118115
// dac iq correction
119116

120117
always @(posedge dac_clk) begin

‎library/axi_dac_interpolate/axi_dac_interpolate.v

Lines changed: 4 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -58,7 +58,6 @@ module axi_dac_interpolate #(
5858
output [15:0] dac_int_data_b,
5959
output dac_valid_out_a,
6060
output dac_valid_out_b,
61-
output hold_last_sample,
6261
output underflow,
6362

6463
input [ 1:0] trigger_i,
@@ -152,8 +151,7 @@ module axi_dac_interpolate #(
152151
wire underflow_a;
153152
wire underflow_b;
154153

155-
wire [ 1:0] lsample_hold_config;
156-
wire sync_stop_channels;
154+
wire stop_sync_channels;
157155

158156
// signal name changes
159157

@@ -206,9 +204,6 @@ module axi_dac_interpolate #(
206204
low_level_trigger <= ~trigger_i_m3 & low_level;
207205
end
208206

209-
assign hold_last_sample = lsample_hold_config[0];
210-
assign sync_stop_channels = lsample_hold_config[1];
211-
212207
assign underflow = underflow_a | underflow_b;
213208

214209
axi_dac_interpolate_filter #(
@@ -220,7 +215,7 @@ module axi_dac_interpolate #(
220215
.dac_data (dac_data_a),
221216
.dac_valid (dac_valid_a),
222217
.dac_valid_out (dac_valid_out_a),
223-
.sync_stop_channels (sync_stop_channels),
218+
.sync_stop_channels (stop_sync_channels),
224219

225220
.dac_enable (dac_enable_a),
226221
.dac_int_data (dac_int_data_a),
@@ -249,7 +244,7 @@ module axi_dac_interpolate #(
249244
.dac_data (dac_data_b),
250245
.dac_valid (dac_valid_b),
251246
.dac_valid_out (dac_valid_out_b),
252-
.sync_stop_channels (sync_stop_channels),
247+
.sync_stop_channels (stop_sync_channels),
253248
.underflow (underflow_b),
254249

255250
.dac_enable (dac_enable_b),
@@ -285,7 +280,7 @@ module axi_dac_interpolate #(
285280
.dac_correction_coefficient_a(dac_correction_coefficient_a),
286281
.dac_correction_coefficient_b(dac_correction_coefficient_b),
287282
.trigger_config (trigger_config),
288-
.lsample_hold_config (lsample_hold_config),
283+
.stop_sync_channels (stop_sync_channels),
289284

290285
.up_rstn (up_rstn),
291286
.up_clk (up_clk),

‎library/axi_dac_interpolate/axi_dac_interpolate_reg.v

Lines changed: 12 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -45,12 +45,12 @@ module axi_dac_interpolate_reg(
4545
output [ 2:0] dac_filter_mask_b,
4646
output dma_transfer_suspend,
4747
output start_sync_channels,
48+
output stop_sync_channels,
4849
output dac_correction_enable_a,
4950
output dac_correction_enable_b,
5051
output [15:0] dac_correction_coefficient_a,
5152
output [15:0] dac_correction_coefficient_b,
5253
output [19:0] trigger_config,
53-
output [ 1:0] lsample_hold_config,
5454
// bus interface
5555

5656
input up_rstn,
@@ -67,24 +67,26 @@ module axi_dac_interpolate_reg(
6767

6868
// internal registers
6969

70-
reg [31:0] up_version = 32'h00020100;
70+
reg [31:0] up_version = {16'h0002, /* MAJOR */
71+
8'h02, /* MINOR */
72+
8'h00}; /* PATCH */
7173
reg [31:0] up_scratch = 32'h0;
7274

7375
reg [31:0] up_interpolation_ratio_a = 32'h0;
7476
reg [ 2:0] up_filter_mask_a = 3'h0;
7577
reg [31:0] up_interpolation_ratio_b = 32'h0;
7678
reg [ 2:0] up_filter_mask_b = 3'h0;
77-
reg [1:0] up_flags = 2'h2;
79+
reg [2:0] up_flags = 3'h2;
7880
reg [1:0] up_config = 2'h0;
7981
reg [15:0] up_correction_coefficient_a = 16'h0;
8082
reg [15:0] up_correction_coefficient_b = 16'h0;
8183
reg [19:0] up_trigger_config = 20'h0;
82-
reg [ 1:0] up_lsample_hold_config = 2'h0;
8384

84-
wire [ 1:0] flags;
85+
wire [ 2:0] flags;
8586

8687
assign dma_transfer_suspend = flags[0];
8788
assign start_sync_channels = flags[1];
89+
assign stop_sync_channels = flags[2];
8890

8991
always @(negedge up_rstn or posedge up_clk) begin
9092
if (up_rstn == 0) begin
@@ -99,7 +101,6 @@ module axi_dac_interpolate_reg(
99101
up_correction_coefficient_a <= 'd0;
100102
up_correction_coefficient_b <= 'd0;
101103
up_trigger_config <= 'd0;
102-
up_lsample_hold_config <= 'h0;
103104
end else begin
104105
up_wack <= up_wreq;
105106
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h1)) begin
@@ -118,7 +119,7 @@ module axi_dac_interpolate_reg(
118119
up_filter_mask_b <= up_wdata[2:0];
119120
end
120121
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h14)) begin
121-
up_flags <= {30'h0,up_wdata[1:0]};
122+
up_flags <= {29'h0,up_wdata[2:0]};
122123
end
123124
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h15)) begin
124125
up_config <= up_wdata[1:0];
@@ -132,9 +133,6 @@ module axi_dac_interpolate_reg(
132133
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h18)) begin
133134
up_trigger_config <= up_wdata[19:0];
134135
end
135-
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h19)) begin
136-
up_lsample_hold_config <= up_wdata[1:0];
137-
end
138136
end
139137
end
140138

@@ -154,12 +152,11 @@ module axi_dac_interpolate_reg(
154152
5'h11: up_rdata <= {29'h0,up_filter_mask_a};
155153
5'h12: up_rdata <= up_interpolation_ratio_b;
156154
5'h13: up_rdata <= {29'h0,up_filter_mask_b};
157-
5'h14: up_rdata <= {30'h0,up_flags};
155+
5'h14: up_rdata <= {29'h0,up_flags};
158156
5'h15: up_rdata <= {30'h0,up_config};
159157
5'h16: up_rdata <= {16'h0,up_correction_coefficient_a};
160158
5'h17: up_rdata <= {16'h0,up_correction_coefficient_b};
161159
5'h18: up_rdata <= {12'h0,up_trigger_config};
162-
5'h19: up_rdata <= {30'h0,up_lsample_hold_config};
163160
default: up_rdata <= 0;
164161
endcase
165162
end else begin
@@ -169,7 +166,7 @@ module axi_dac_interpolate_reg(
169166
end
170167

171168
up_xfer_cntrl #(
172-
.DATA_WIDTH(128)
169+
.DATA_WIDTH(127)
173170
) i_xfer_cntrl (
174171
.up_rstn (up_rstn),
175172
.up_clk (up_clk),
@@ -178,8 +175,7 @@ module axi_dac_interpolate_reg(
178175
up_correction_coefficient_b,// 16
179176
up_correction_coefficient_a,// 16
180177
up_trigger_config, // 20
181-
up_lsample_hold_config, // 2
182-
up_flags, // 2
178+
up_flags, // 3
183179
up_interpolation_ratio_b, // 32
184180
up_interpolation_ratio_a, // 32
185181
up_filter_mask_b, // 3
@@ -193,8 +189,7 @@ module axi_dac_interpolate_reg(
193189
dac_correction_coefficient_b, // 16
194190
dac_correction_coefficient_a, // 16
195191
trigger_config, // 20
196-
lsample_hold_config, // 2
197-
flags, // 2
192+
flags, // 3
198193
dac_interpolation_ratio_b, // 32
199194
dac_interpolation_ratio_a, // 32
200195
dac_filter_mask_b, // 3

‎projects/m2k/common/m2k_bd.tcl

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -265,7 +265,6 @@ ad_connect axi_dac_interpolate/trigger_la logic_analyzer/trigger_out_adc
265265

266266
ad_connect axi_dac_interpolate/dac_valid_out_a axi_ad9963/dma_valid_i
267267
ad_connect axi_dac_interpolate/dac_valid_out_b axi_ad9963/dma_valid_q
268-
ad_connect axi_dac_interpolate/hold_last_sample axi_ad9963/hold_last_sample
269268

270269
ad_connect /axi_ad9963/tx_data txd
271270
ad_connect /axi_ad9963/tx_iq txiq

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