axi_dmac: Use AXI3 for DMAC in Intel projects

The buffers inside the interconnect are sized based on maximum burst sizes
the masters can produce.
For AXI4 the max burst size is 128 but for these projects for the
default burst size of 128 bytes the DMACs are creating only burst of 8 or
16 beats depending on the bus width (128bits and 64 bits respectively).

These burst sizes can fit in the AXI3 protocol where the max burst
length is 16. Therefore the interconnect will be reduced.

The observed reduction is around 4 Mb of block RAM per project.
Another benefit is a better timing closure,
since these buffers reside in the DDR3 clock domain.

Author: ronagyl

library/axi_dmac/axi_dmac_hw.tcl

@@ -91,7 +91,7 @@ foreach {suffix group} { \
     { "0:Memory-Mapped AXI" "1:Streaming AXI" "2:FIFO Interface" }
   set_parameter_property DMA_TYPE_$suffix GROUP $group
 
-  add_parameter  DMA_AXI_PROTOCOL_$suffix INTEGER 0
+  add_parameter  DMA_AXI_PROTOCOL_$suffix INTEGER 1
   set_parameter_property DMA_AXI_PROTOCOL_$suffix DISPLAY_NAME "AXI Protocol"
   set_parameter_property DMA_AXI_PROTOCOL_$suffix HDL_PARAMETER true
   set_parameter_property DMA_AXI_PROTOCOL_$suffix ALLOWED_RANGES { "0:AXI4" "1:AXI3" }