updated shell link #308
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updated shell link #308
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AWSwinefred
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Apr 19, 2017
kyyalama2
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May 24, 2022
* Added a fix for 64 byte aligned addresses * Added FATAL message and removed unaligned addresses in test * Removed display statements used for debug * Removed old code which is no longer required * Corrected spaces * Added back DMA_TEST define to makefiles (#308) Merging into AWShimasajja-dma-fatal-add branch
kyyalama2
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that referenced
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May 24, 2022
* Added a fix for 64 byte aligned addresses * Added FATAL message and removed unaligned addresses in test * Removed display statements used for debug * Removed old code which is no longer required * Corrected spaces * Added back DMA_TEST define to makefiles (#308) Merging into AWShimasajja-dma-fatal-add branch * Update README.md -Added documentation to disable unused DDR controllers. * Update README.md -Changed font for Design Changes and Test Changes * Update README.md * Update README.md Updated one more commit * Update README.md * Update README.md * Update README.md
kyyalama2
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that referenced
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May 24, 2022
* Added a fix for 64 byte aligned addresses * Added FATAL message and removed unaligned addresses in test * Removed display statements used for debug * Removed old code which is no longer required * Corrected spaces * Added back DMA_TEST define to makefiles (#308) Merging into AWShimasajja-dma-fatal-add branch * Added HW/SW co-simulation and HW test * Added new SV URAM test * Removed extra space * Update README.md -Added documentation as to how to run with different simulators. * Update README.md Changed sourc to source. * Update test_dram_dma.sv Added comments * Update test_uram_example.c -Updated comments to add a value * Added URAM example test * Changed cl_uram to cl_uram_example * Added cl_uram_example to Jenkinsfile * Removed cl_uram_example from dcp_recipe and runtime_sw_cl_names as this is run as part of developper flow testing * Aw shimasajja write combine (#319) * Initial commit HW/SW co-simulation for cl_dram_dma example * Fixed TEST PASS/FAIL signatures * Backed up changes to test_dram_dma.c * Added makefile option to compile test_dram_dma_hwsw_cosim * Update RTL_Simulating_CL_Designs.md Added documentation for HW/SW cosimulation of cl_dram_dma example. * Update README.md Added documentation for cl_dram_dma_hwsw_cosim example. * Update README.md * Update README.md Update README to fix documentation issues. * Update README.md More fixes to the documentation. * Made changes from the code review * Updated error_count value * Added missing memcmp function * Fixed compile errors in C test * Added define for test_main. Updated main in test_hello_world * Added a common file for common dma functions between test_dram_dma and test_dram_dma_hwsw_cosim * Moved common functions between the two files to common_dma.c * Changed usage function name * Moved main definition back to the 'C' files * Added Amazon header * Changed the structure again to include .h file * Created new fpga_pci_sv.c and moved all the function definitions to avoid multiple definition errors when includign fpga_pci_sv.h. Updated Makefiles to reflect this change * Changed the way common_dma.h is included * Updated test_sims.py with new C Test * Pushed Kiran's write combine changes * Removed skip python command * Added write combine simulation test * Fixed more merge issues * Update RTL_Simulating_CL_Designs.md -Added documentation for poke_pcis_wc * Update RTL_Simulating_CL_Designs.md -Fixed a typo * Removed extra space * Update test_peek_poke_wc.sv -Fixed header for test_peek_poke_wc.sv * Update test_sims.py Fixed command * Update test_peek_poke_wc.sv -Added documentation * Update test_uram_example.c -Added documentation * Update test_uram_example.sv -Added documentation
kyyalama2
pushed a commit
that referenced
this pull request
May 24, 2022
* Added a fix for 64 byte aligned addresses * Added FATAL message and removed unaligned addresses in test * Removed display statements used for debug * Removed old code which is no longer required * Corrected spaces * Added back DMA_TEST define to makefiles (#308) Merging into AWShimasajja-dma-fatal-add branch * Update README.md * Update README.md -Made each test a section * Update README.md -Changed wording * Update README.md Removed line before link * Update README.md -Removed .md at the end * Update README.md -Updated link name * Update README.md -Changed the structure of the README * Update README.md -Removed information about number of tests as that information can be found in below sections * Update README.md -Removed Details * Create README.md Created README for DRAM DMA example. * Update README.md -More updates * Update README.md Changed description for SDA AXIL interface * Update README.md Fixed link for RTL_simulating_CL_Designs * Update README.md Fixed link for RTL_Simulating_CL_Designs * Update RTL_Simulating_CL_Designs.md -Added missed documentation * Update RTL_Simulating_CL_Designs.md Added missing functions * Update RTL_Simulating_CL_Designs.md -Added more missing API * Update RTL_Simulating_CL_Designs.md Corrected grammatic mistakes. * Update README.md -Changed IPI link * Update README.md -Updated IPI link * Update README.md -Added section on Dump Waves * Update README.md -Added section on dumping waves * Aw shimasajj v1.4 documentation 1 (#346) * Aw shimasajja uram test [needed for v1.3.7] (#341) * Added a fix for 64 byte aligned addresses * Added FATAL message and removed unaligned addresses in test * Removed display statements used for debug * Removed old code which is no longer required * Corrected spaces * Added back DMA_TEST define to makefiles (#308) Merging into AWShimasajja-dma-fatal-add branch * Added HW/SW co-simulation and HW test * Added new SV URAM test * Removed extra space * Update README.md -Added documentation as to how to run with different simulators. * Update README.md Changed sourc to source. * Update test_dram_dma.sv Added comments * Update test_uram_example.c -Updated comments to add a value * Added URAM example test * Changed cl_uram to cl_uram_example * Added cl_uram_example to Jenkinsfile * Removed cl_uram_example from dcp_recipe and runtime_sw_cl_names as this is run as part of developper flow testing * Aw shimasajja write combine (#319) * Initial commit HW/SW co-simulation for cl_dram_dma example * Fixed TEST PASS/FAIL signatures * Backed up changes to test_dram_dma.c * Added makefile option to compile test_dram_dma_hwsw_cosim * Update RTL_Simulating_CL_Designs.md Added documentation for HW/SW cosimulation of cl_dram_dma example. * Update README.md Added documentation for cl_dram_dma_hwsw_cosim example. * Update README.md * Update README.md Update README to fix documentation issues. * Update README.md More fixes to the documentation. * Made changes from the code review * Updated error_count value * Added missing memcmp function * Fixed compile errors in C test * Added define for test_main. Updated main in test_hello_world * Added a common file for common dma functions between test_dram_dma and test_dram_dma_hwsw_cosim * Moved common functions between the two files to common_dma.c * Changed usage function name * Moved main definition back to the 'C' files * Added Amazon header * Changed the structure again to include .h file * Created new fpga_pci_sv.c and moved all the function definitions to avoid multiple definition errors when includign fpga_pci_sv.h. Updated Makefiles to reflect this change * Changed the way common_dma.h is included * Updated test_sims.py with new C Test * Pushed Kiran's write combine changes * Removed skip python command * Added write combine simulation test * Fixed more merge issues * Update RTL_Simulating_CL_Designs.md -Added documentation for poke_pcis_wc * Update RTL_Simulating_CL_Designs.md -Fixed a typo * Removed extra space * Update test_peek_poke_wc.sv -Fixed header for test_peek_poke_wc.sv * Update test_sims.py Fixed command * Update test_peek_poke_wc.sv -Added documentation * Update test_uram_example.c -Added documentation * Update test_uram_example.sv -Added documentation * Adding 3ddr example for SDAccel as received from xilinx [needed for v1.3.7] (#339) * Adding 3ddr example for SDAccel as received from xilinx. updated Jenkins file to include this in customer flow testing. updated Jenkins file with ddr_combo parameter modified: Jenkinsfile new file: SDAccel/examples/aws/kernel_3ddr_bandwidth/Makefile new file: SDAccel/examples/aws/kernel_3ddr_bandwidth/description.json new file: SDAccel/examples/aws/kernel_3ddr_bandwidth/src/kernel.cl new file: SDAccel/examples/aws/kernel_3ddr_bandwidth/src/kernel_global_bandwidth.cpp * Adding placeholder header for source files modified: SDAccel/examples/aws/kernel_3ddr_bandwidth/Makefile modified: SDAccel/examples/aws/kernel_3ddr_bandwidth/src/kernel.cl modified: SDAccel/examples/aws/kernel_3ddr_bandwidth/src/kernel_global_bandwidth.cpp * removing license headers since we received these files from xilinx and adding them to exclusion in src_header_check modified: SDAccel/examples/aws/kernel_3ddr_bandwidth/Makefile modified: SDAccel/examples/aws/kernel_3ddr_bandwidth/src/kernel.cl modified: SDAccel/examples/aws/kernel_3ddr_bandwidth/src/kernel_global_bandwidth.cpp modified: shared/lib/check_src_headers.py * 1. Removed 3ddr test from 2017.1 in Jenkins for PR qual runs since it's not supported. 2. Adding a helloworld_ocl runtime example so developers can directly run a executable on F1 instance. 3. changed permission on description.json file to match other examples. modified: Jenkinsfile modified: SDAccel/README.md new file: SDAccel/examples/aws/helloworld_ocl_runtime/README.md new file: SDAccel/examples/aws/helloworld_ocl_runtime/helloworld new file: SDAccel/examples/aws/helloworld_ocl_runtime/helloworld_ocl_afi_id.txt new file: SDAccel/examples/aws/helloworld_ocl_runtime/helloworld_ocl_agfi_id.txt new file: SDAccel/examples/aws/helloworld_ocl_runtime/vector_addition.hw.xilinx_aws-vu9p-f1_dynamic_5_0.awsxclbin modified: SDAccel/examples/aws/kernel_3ddr_bandwidth/description.json * updating README for SDAccel helloworld runtime fixing broken link to SDAccel readme.md * updating exclude filelist for license header check Added the following files to license checker check exclusion list -"SDAccel/examples/aws/helloworld_ocl_runtime/helloworld", -"SDAccel/examples/aws/helloworld_ocl_runtime/vector_addition.hw.xilinx_aws-vu9p-f1_dynamic_5_0.awsxclbin" * updated top.*.f files in cl_dram_dma & cl_hello_world to compile with AMI V1.4 Added missing IP into *.f. modified: hdk/cl/examples/cl_dram_dma/verif/scripts/top.ies.f modified: hdk/cl/examples/cl_dram_dma/verif/scripts/top.questa.f modified: hdk/cl/examples/cl_dram_dma/verif/scripts/top.vcs.f modified: hdk/cl/examples/cl_hello_world/verif/scripts/top.ies.f modified: hdk/cl/examples/cl_hello_world/verif/scripts/top.questa.f modified: hdk/cl/examples/cl_hello_world/verif/scripts/top.vcs.f * Update top.vcs.f Added missing ${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/hdl/axi_clock_converter_v2_1_vl_rfs.v * Update top.ies.f -Added missing incdir+${CL_ROOT}/design/axi_crossbar_0 * Increased delay after power up as the latest version of DDR models seem to need more time to initialize for IES * 1. Adding license headers to kernel_3ddr_bandwidth source files 2. removed these source files from exclude list in check_src_headers 3. updated setup_test_enc.sh to run the setup_gui.sh script for every tests 4. Added a test_gui_script pytest to be included in jenkins later modified: SDAccel/examples/aws/kernel_3ddr_bandwidth/Makefile modified: SDAccel/examples/aws/kernel_3ddr_bandwidth/src/kernel.cl modified: SDAccel/examples/aws/kernel_3ddr_bandwidth/src/kernel_global_bandwidth.cpp modified: shared/lib/check_src_headers.py modified: shared/tests/bin/setup_test_env.sh new file: shared/tests/test_gui_script.py * Update kernel.cl * Update kernel_global_bandwidth.cpp * license header update. pulled out 2 forward slashes at the end modified: SDAccel/examples/aws/kernel_3ddr_bandwidth/src/kernel.cl modified: SDAccel/examples/aws/kernel_3ddr_bandwidth/src/kernel_global_bandwidth.cpp * Top level Documentation Improvements [v1.4] (#342) * Update README.md * Add files via upload * Update README.md * Update README.md * Update README.md * Update README.md * Update README.md * Update README.md * Update RELEASE_NOTES.md * Update RELEASE_NOTES.md * Update RELEASE_NOTES.md * Update README.md * Update README.md (#345) Changed the reading flow, updated to narrative (vs bullet points) mainly in the getting started section, and unified the nomenclature and updated the messaging. +spelling * Update RELEASE_NOTES.md added TODO section. Nomenclature changes and language/flow updates * Update RELEASE_NOTES.md Fixed broken link fails * README.md -Added README for test_uram_example simulation example. * Update README.md * Update README.md -Made each test a section * Update README.md -Changed wording * Update README.md Removed line before link * Update README.md -Removed .md at the end * Update README.md -Updated link name * Update README.md -Changed the structure of the README * Update README.md -Removed information about number of tests as that information can be found in below sections * Update README.md -Removed Details * Create README.md Created README for DRAM DMA example. * Update README.md -More updates * Update README.md Changed description for SDA AXIL interface * Update README.md Fixed link for RTL_simulating_CL_Designs * Update README.md Fixed link for RTL_Simulating_CL_Designs * Update RTL_Simulating_CL_Designs.md -Added missed documentation * Update RTL_Simulating_CL_Designs.md Added missing functions * Update RTL_Simulating_CL_Designs.md -Added more missing API * Update RTL_Simulating_CL_Designs.md Corrected grammatic mistakes. * Update README.md -Changed IPI link * Update README.md -Updated IPI link * Update README.md -Added section on Dump Waves * Update README.md -Added section on dumping waves * README.md -Added README for test_uram_example simulation example. * Update README.md -Updated software/runtime link * Update README.md -Corrected from feedback * Update README.md -Made changes from the review * Update RTL_Simulating_CL_Designs.md -Added Cadence Simulator in the document * Update README.md -Documentation changes from Review * Update README.md -Added more details to verif section
kyyalama2
pushed a commit
that referenced
this pull request
May 24, 2022
* Added a fix for 64 byte aligned addresses * Added FATAL message and removed unaligned addresses in test * Removed display statements used for debug * Removed old code which is no longer required * Corrected spaces * Added back DMA_TEST define to makefiles (#308) Merging into AWShimasajja-dma-fatal-add branch * Added backdoor loading files * Updated backdoor loading * Tie off the AWBURST and ARBURST ports * Added code to tie off burst ports * Added axi4_bfm * AXI memory model updates * Updates for AXI mem model. * Removed defines for Micron model debug * Added documentation * Added DDR backdoor loading tests and AXI memory model tests * Sample memory text file * Removed FAST mode from cadence makefile * Fixed configuration in backdoor loading text file * AXI memory model changes and DDR backdoor loading fixes * Added code to name generate block * Update README.md Added description for AXI memory model and DDR backdoor loading. * Update README.md Added documentation for each test. * Update README.md Added italics * Update README.md More fixes * More DDR backdoor loading test changes * backdoor access files * Added patch to rename generate block in sh_ddr * Fixed DMA backdoor loading tests * Fix for ready signals * Added header to .mem files * Added headers * Removed axi4_bfm. Not needed anymore * Removed old backdoor loading test file * Update README.md -Test covered in ddr backdoor walking ones * Added headers * Encryption changes * Updated customer flow simulation testing * Updated common makefile to move sed commands * Moved sed commands away from target * Fixed Makefile commands
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