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Merged
merged 6 commits into from
Aug 1, 2019
Merged

Rc v1 4 10 #463

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148517c
Patching HDK 1.4.8
AWSaalluri Apr 17, 2019
6a9e299
RELEASE V1.4.9
AWSaalluri May 13, 2019
ec1f87c
Release V1.4.10
AWSaalluri Jul 29, 2019
1a15ce8
Merge branch 'master' into RC_v1_4_10
AWSaalluri Jul 30, 2019
ac17874
updating exec permisions
AWSaalluri Jul 30, 2019
a4b4275
Merge branch 'RC_v1_4_10' of github.com:aws/aws-fpga into RC_v1_4_10
AWSaalluri Jul 30, 2019
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2 changes: 1 addition & 1 deletion .gitmodules
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
[submodule "SDAccel/examples/xilinx_2018.2"]
path = SDAccel/examples/xilinx_2018.2
url = https://github.com/Xilinx/SDAccel_Examples.git
branch = 2018.2
branch = 2018.2_xdf
[submodule "SDAccel/examples/xilinx_2018.3"]
path = SDAccel/examples/xilinx_2018.3
url = https://github.com/Xilinx/SDAccel_Examples.git
Expand Down
14 changes: 2 additions & 12 deletions ERRATA.md
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Expand Up @@ -5,23 +5,13 @@
[Shell\_04261818_Errata](./hdk/docs/AWS_Shell_ERRATA.md)

## HDK
* Multiple SDE instances per CL is not supported in this release. Support planned for future release.
* Multiple SDE instances per CL is not supported in this release. Support is planned for a future release.
* DRAM Data retention is not supported for CL designs with less than 4 DDRs enabled
* Combinatorial loops in CL designs are not supported.
* [Automatic Traffic Generator (ATG)](./hdk/cl/examples/cl_dram_dma/design/cl_tst.sv) in SYNC mode does not wait for write response transaction before issuing read transactions. The fix for this issue is planned in a future release.

## SDK

## SDAccel (For additional restrictions see [SDAccel ERRATA](./SDAccel/ERRATA.md))
* Virtual Ethernet is not supported when using SDAccel
* DRAM Data retention is not supported for kernels that provision less than 4 DDRs
* Combinatorial loops in CL designs are not supported.
* When using [Xilinx runtime(XRT) version 2018.3.3.1](https://github.com/Xilinx/XRT/releases/tag/2018.3.3.1) or [AWS FPGA Developer AMI Version 1.6.0](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) your host application could fail with following error:

```
: symbol lookup error: /opt/xilinx/xrt/lib/libxrt_aws.so: undefined symbol: uuid_parse!

```
The SDAccel examples included in the developer kit use a SDAccel configuration file [sdaccel.ini]. To workaround this error please copy the SDAccel configuration file [sdaccel.ini](SDAccel/examples/aws/helloworld_ocl_runtime/sdaccel.ini) to your executable directory and try executing your application again.
AWS is working with Xilinx to release a XRT patch to fix this issue.

* Combinatorial loops in CL designs are not supported.
38 changes: 26 additions & 12 deletions Jenkinsfile
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Expand Up @@ -46,7 +46,7 @@ boolean test_all_sdaccel_examples_fdf = params.get('test_all_sdaccel_examples_fd
boolean test_helloworld_sdaccel_example_fdf = params.get('test_helloworld_sdaccel_example_fdf')
boolean disable_runtime_tests = params.get('disable_runtime_tests')

def runtime_sw_cl_names = ['cl_dram_dma', 'cl_hello_world']
def runtime_sw_cl_names = ['cl_dram_dma', 'cl_hello_world', 'cl_sde']
def dcp_recipe_cl_names = ['cl_dram_dma', 'cl_hello_world']
def dcp_recipe_scenarios = [
// Default values are tested in FDF: A0-B0-C0-DEFAULT
Expand All @@ -68,14 +68,15 @@ def fdf_test_names = [
'cl_dram_dma[A1-B0-C0-DEFAULT]',
'cl_hello_world[A0-B0-C0-DEFAULT]',
'cl_hello_world_vhdl',
'cl_sde[A0-B0-C0-DEFAULT]',
'cl_uram_example[2]',
'cl_uram_example[3]',
'cl_uram_example[4]'
]

boolean debug_dcp_gen = params.get('debug_dcp_gen')
if (debug_dcp_gen) {
fdf_test_names = ['cl_hello_world[A0-B0-C0-DEFAULT]']
fdf_test_names = ['cl_sde[A0-B0-C0-DEFAULT]']
test_markdown_links = false
test_sims = false
test_runtime_software = false
Expand Down Expand Up @@ -158,19 +159,19 @@ def sdaccel_example_default_map = [
def simulator_tool_default_map = [
'2017.4' : [
'vivado': 'xilinx/SDx/2017.4_04112018',
'vcs': 'vcs-mx/L-2016.06-1',
'vcs': 'synopsys/vcs-mx/M-2017.03-SP2-11',
'questa': 'questa/10.6b',
'ies': 'incisive/15.20.063'
],
'2018.2' : [
'vivado': 'xilinx/SDx/2018.2_06142018',
'vcs': 'vcs-mx/N-2017.12-SP1-1',
'vcs': 'synopsys/vcs-mx/N-2017.12-SP2',
'questa': 'questa/10.6c_1',
'ies': 'incisive/15.20.063'
],
'2018.3' : [
'vivado': 'xilinx/SDx/2018.3_1207',
'vcs': 'vcs-mx/N-2017.12-SP1-1',
'vcs': 'synopsys/vcs-mx/N-2017.12-SP2',
'questa': 'questa/10.6c_1',
'ies': 'incisive/15.20.063'
]
Expand All @@ -196,7 +197,7 @@ def get_task_label(Map args=[ : ]) {
}
if (params.internal_simulations) {
echo "internal simulation agent requested"
task_label = 'f1'
task_label = 'f1_3rd_party_sims'
}

echo "Label Requested: $task_label"
Expand Down Expand Up @@ -492,7 +493,7 @@ if (test_fpga_tools) {
if (test_sims) {
all_tests['Run Sims'] = {
stage('Run Sims') {
def cl_names = ['cl_uram_example', 'cl_dram_dma', 'cl_hello_world', 'cl_sde']
def cl_names = ['cl_vhdl_hello_world', 'cl_uram_example', 'cl_dram_dma', 'cl_hello_world', 'cl_sde']
def simulators = ['vivado']
def sim_nodes = [:]
if(params.internal_simulations) {
Expand All @@ -505,6 +506,15 @@ if (test_sims) {
String xilinx_version = y
String cl_name = x
String simulator = z
if((cl_name == 'cl_vhdl_hello_world') && (simulator == 'ies')) {
println ("Skipping Simulator: ${simulator} CL: ${cl_name}")
continue;
}
String cl_dir_name = cl_name
if(cl_name == 'cl_vhdl_hello_world') {
cl_dir_name = "cl_hello_world_vhdl"
}

String node_name = "Sim ${cl_name} ${xilinx_version} ${simulator}"
String key = "test_${cl_name}__"
String report_file = "test_sims_${cl_name}_${xilinx_version}.xml"
Expand All @@ -525,27 +535,29 @@ if (test_sims) {
sh """
set -e
module purge
module load python/2.7.9
module load python/3.7.2
module load python/2.7.14
module load batch
module load ${vivado_module}
module load ${vcs_module}
module load ${questa_module}
module load ${ies_module}
source $WORKSPACE/hdk_setup.sh
python2.7 -m pytest -v $WORKSPACE/hdk/tests/simulation_tests/test_sims.py -k \"${key}\" --junit-xml $WORKSPACE/${report_file} --simulator ${simulator}
python2.7 -m pytest -v $WORKSPACE/hdk/tests/simulation_tests/test_sims.py -k \"${key}\" --junit-xml $WORKSPACE/${report_file} --simulator ${simulator} --batch 'TRUE'
"""
} else {
sh """
set -e
source $WORKSPACE/shared/tests/bin/setup_test_hdk_env.sh
python2.7 -m pytest -v $WORKSPACE/hdk/tests/simulation_tests/test_sims.py -k \"${key}\" --junit-xml $WORKSPACE/${report_file} --simulator ${simulator}
python2.7 -m pytest -v $WORKSPACE/hdk/tests/simulation_tests/test_sims.py -k \"${key}\" --junit-xml $WORKSPACE/${report_file} --simulator ${simulator} --batch 'FALSE'
"""
}
} catch (exc) {
echo "${node_name} failed"
throw exc
} finally {
run_junit(report_file)
archiveArtifacts artifacts: "hdk/cl/examples/${cl_name}/**/*.sim.log", fingerprint: true
archiveArtifacts artifacts: "hdk/cl/examples/${cl_dir_name}/**/*.sim.log", fingerprint: true
}
}
}
Expand Down Expand Up @@ -923,13 +935,15 @@ if (test_helloworld_sdaccel_example_fdf || test_all_sdaccel_examples_fdf) {
sh """
set -e
source $WORKSPACE/shared/tests/bin/setup_test_build_sdaccel_env.sh
python2.7 -m pytest -v $WORKSPACE/SDAccel/tests/test_find_sdaccel_examples.py --junit-xml $WORKSPACE/${report_file}
python2.7 -m pytest -v $WORKSPACE/SDAccel/tests/test_find_sdaccel_examples.py --junit-xml $WORKSPACE/${report_file} --xilinxVersion ${xilinx_version}
"""
} catch (exc) {
echo "Could not find tests. Please check the repository."
throw exc
} finally {
run_junit(report_file)
archiveArtifacts artifacts: "${sdaccel_examples_list}.*", fingerprint: true

}

// Only run the hello world test by default
Expand Down
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