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@deeppat deeppat commented Feb 7, 2020

  • Added Xilinx 2019.2 toolset support
  • Enabled Vitis Runs
  • Updated XRT link for 2019.1
  • Update ERRATA.md
    • Add errata that CL cannot connect shell generated clock directly to BUFG in CL.

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* Added Xilinx 2019.2 toolset support
* Enabled Vitis Runs
* Updated XRT link for 2019.1
* Update ERRATA.md
  * Add errata that CL cannot connect shell generated clock directly to BUFG in CL.
@kristopk kristopk merged commit 5e9f4cb into master Feb 12, 2020
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3 participants