aws · TrahStevAmz · Jan 29, 2025 · Jan 28, 2025
diff --git a/RELEASE_NOTES.md b/RELEASE_NOTES.md
@@ -1,5 +1,10 @@
 # F2 Developer Kit Release Notes
 
+## v2.0.3
+* Releasing fpga_mgmt_examples to demonstrate how the FPGA Management C API is used to perform FPGA image slot load and clear operations.
+* Releasing the PacketGen Dual Instance Loopback example to the SDK Virtual Ethernet Application.
+* Fixing the clkgen CLIs to prevent the configuration of clock groups that were removed from the AWS_CLK_GEN IP in customer designs.
+
 ## v2.0.2
 Updates for initial release of ReadTheDocs documentation and to re-enable tests for XSIM.
 

diff --git a/User_Guide_AWS_EC2_FPGA_Development_Kit.md b/User_Guide_AWS_EC2_FPGA_Development_Kit.md
@@ -12,14 +12,10 @@ The development kit includes example designs to get you familiar with developing
     - [AWS Shells](#aws-shells)
     - [Hardware Development Kit (HDK)](#hardware-development-kit-hdk)
     - [Software-Defined Development Environment](#software-defined-development-environment)
-      - [Hardware Emulation](#hardware-emulation)
-      - [Host Application and FPGA Binary Builds](#host-application-and-fpga-binary-builds)
-      - [AFI Generation](#afi-generation)
     - [Additional Vitis Documentation](#additional-vitis-documentation)
     - [FPGA Developer AMI](#fpga-developer-ami)
   - [Getting Started](#getting-started)
     - [Getting Familiar with AWS](#getting-familiar-with-aws)
-    - [Customer Hardware Development](#customer-hardware-development)
   - [Next Steps](#next-steps)
 
 ## AWS EC2 F2 Instance Overview
@@ -34,7 +30,7 @@ This documentation is relevant to F2 only. Therefore, it applies to all branches
 
 ### 2nd Generation On-Cloud FPGA Accelerator Card
 
-![f2_instances](./shared/assets/accel_card_specs.png)
+![f2_instances](./shared/assets/accel_card_specs_20250110.png)
 
 ### Comparison to F1
 
@@ -99,7 +95,7 @@ Our scripts require a minimum Python version of 3.10, under `/usr/bin/env python
 
 The software-defined development environment allows customers to compile their C/C++/OpenCL code into AFIs and use C/C++/OpenCL APIs to interface with the accelerator, running on the FPGA. Software developers with little or no FPGA experience will be able to quickly familiarize themselves with the development experience that accelerates cloud applications. The optimized compiler, Vitis, allows easy F2 accelerator development using C/C++/OpenCL and/or Verilog/VHDL.
 
-The F2 developer kit provides development tools for Vitis hardware emulation, example host applications, and FPGA Binary builds, followed by AFI generation.
+Currently, the F2 developer kit provides development tools for Vitis hardware emulation.
 
 To get started, please see the [README for a hello world accelerator example](./vitis/README.md)
 

diff --git a/docs-rtd/source/RELEASE_NOTES.rst b/docs-rtd/source/RELEASE_NOTES.rst
@@ -1,10 +1,20 @@
 F2 Developer Kit Release Notes
 ==============================
 
+.. _v203:
+
+v2.0.3
+------
+
+* Releasing fpga_mgmt_examples to demonstrate how the FPGA Management C API is used to perform FPGA image slot load and clear operations.
+* Releasing the PacketGen Dual Instance Loopback example to the SDK Virtual Ethernet Application.
+* Fixing the clkgen CLIs to prevent the configuration of clock groups that were removed from the AWS_CLK_GEN IP in customer designs.
+
 .. _v202:
 
 v2.0.2
 ------
+
 Updates for initial release of ReadTheDocs documentation and to re-enable tests for XSIM.
 
 .. _v201:

diff --git a/docs-rtd/source/User_Guide_AWS_EC2_FPGA_Development_Kit.rst b/docs-rtd/source/User_Guide_AWS_EC2_FPGA_Development_Kit.rst
@@ -10,7 +10,7 @@ developing for AWS EC2 FPGA Instances.
 
     - `Instance Types <#instance-types>`__
     - `2nd Generation On-Cloud FPGA Accelerator
-      Card <#2nd-generation-on-cloud-fpga-accelerator-card>`__
+      Card <#second-generation-on-cloud-fpga-accelerator-card>`__
     - `Comparison to F1 <#comparison-to-f1>`__
 
   - `AWS EC2 F2 FPGA Development
@@ -22,22 +22,18 @@ developing for AWS EC2 FPGA Instances.
     - `Software-Defined Development
       Environment <#software-defined-development-environment>`__
 
-      - `Hardware Emulation <#hardware-emulation>`__
-      - `Host Application and FPGA Binary
-        Builds <#host-application-and-fpga-binary-builds>`__
-      - `AFI Generation <#afi-generation>`__
-
     - `Additional Vitis
       Documentation <#additional-vitis-documentation>`__
     - `FPGA Developer AMI <#fpga-developer-ami>`__
 
   - `Getting Started <#getting-started>`__
 
     - `Getting Familiar with AWS <#getting-familiar-with-aws>`__
-    - `Customer Hardware Development <#customer-hardware-development>`__
 
   - `Next Steps <#next-steps>`__
 
+.. _aws-ec2-f2-instance-overview:
+
 AWS EC2 F2 Instance Overview
 ----------------------------
 
@@ -61,18 +57,22 @@ branches on the `GitHub repo <https://github.com/aws/aws-fpga>`__
 prefixed with ``f2``. Any branches not prefixed f2 in their name are not
 referred to in this documentation.
 
+.. _instance-types:
+
 Instance Types
 ~~~~~~~~~~~~~~
 
 |f2_instances|
 
-.. _2nd-generation-on-cloud-fpga-accelerator-card:
+.. _second-generation-on-cloud-fpga-accelerator-card:
 
 2nd Generation On-Cloud FPGA Accelerator Card
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 |image1|
 
+.. _comparison-to-f1:
+
 Comparison to F1
 ~~~~~~~~~~~~~~~~
 
@@ -81,6 +81,8 @@ Comparison to F1
 AWS EC2 F2 FPGA Development Kit
 -------------------------------
 
+.. _development-environments-user-guide:
+
 Development Environments
 ~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -100,9 +102,9 @@ supported in the development kit.
     - Typical Developer
   * - `Hardware accelerator development using Vivado <./hdk/README.html>`__
     - This environment supports the Hardware Development Kit (HDK) design flow,
-      which empowers FPGA developers to create accelerator designs from scratch, 
-      using HDL source code and IPs. The AMD Vivado tool synthesizes, implements, 
-      and generates the Design Check Point (DCP) file used in F2 AFI creation. 
+      which empowers FPGA developers to create accelerator designs from scratch,
+      using HDL source code and IPs. The AMD Vivado tool synthesizes, implements,
+      and generates the Design Check Point (DCP) file used in F2 AFI creation.
       AWS FPGA developers benefit from the suite of scripts supplied in the HDK
       that help to automate different design steps. This allows for flexibility
       in architecting, implementing, and optimizing accelerator designs while
@@ -112,15 +114,15 @@ supported in the development kit.
     - Simulation
     - Hardware developers with advanced FPGA experience
   * - `Hardware accelerator development using Vitis <./vitis/README.html>`__
-    - This environment supports the Vitis design flow, 
+    - This environment supports the Vitis design flow,
       which enables software developers to write C++ code,
-      which may then be compiled into RTL and used in 
-      cycle-accurate hardware simulation. After it may 
-      then be built into an accelerator design. This step 
-      is not necessary, but is encouraged. Vitis may also 
-      be used to implement accelerator designs from scratch, 
-      using HDL and IPs directly, similar to Vivado. Vitis 
-      offers additional analysis tools to aid in the 
+      which may then be compiled into RTL and used in
+      cycle-accurate hardware simulation. After it may
+      then be built into an accelerator design. This step
+      is not necessary, but is encouraged. Vitis may also
+      be used to implement accelerator designs from scratch,
+      using HDL and IPs directly, similar to Vivado. Vitis
+      offers additional analysis tools to aid in the
       refinement of designs.
     - C/C++/Verilog/System Verilog/VHDL
     - XDMA Engine (coming soon)
@@ -133,6 +135,8 @@ environment using 2024.1 AMD tools with their own licenses. Refer to
 this guide `here <./hdk/docs/on_premise_licensing_help.html>`__ for
 licensing requirements.
 
+.. _aws-shells:
+
 AWS Shells
 ~~~~~~~~~~
 
@@ -168,6 +172,9 @@ table below details the released shell version and its main features.
     - 0x10212415
     - Shell with no built-in DMA engine (40% smaller shell footprint).
 
+
+.. _hardware-development-kit-hdk:
+
 Hardware Development Kit (HDK)
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -214,7 +221,9 @@ Our scripts require a minimum Python version of 3.10, under
   * - Tool
     - Minimum Version
   * - Python
-    - 3.10+ 
+    - 3.10+
+
+.. _software-defined-development-environment:
 
 Software-Defined Development Environment
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -227,13 +236,14 @@ themselves with the development experience that accelerates cloud
 applications. The optimized compiler, Vitis, allows easy F2 accelerator
 development using C/C++/OpenCL and/or Verilog/VHDL.
 
-The F2 developer kit provides development tools for Vitis hardware
-emulation, example host applications, and FPGA Binary builds, followed
-by AFI generation.
+Currently, the F2 developer kit provides development tools for Vitis hardware
+emulation.
 
 To get started, please see the `README for a hello world accelerator
 example <./vitis/README.html>`__
 
+.. _fpga-developer-ami:
+
 FPGA Developer AMI
 ~~~~~~~~~~~~~~~~~~
 
@@ -268,9 +278,13 @@ types <https://aws.amazon.com/ec2/instance-types/#General_Purpose>`__.
 Note that the tools used by the HDK are only supported on x86-based EC2
 instances (Graviton-based instances are not compatible with the tools).
 
+.. _getting-started:
+
 Getting Started
 ---------------
 
+.. _getting-familiar-with-aws:
+
 Getting Familiar with AWS
 ~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -281,6 +295,8 @@ and `AWS S3 <https://aws.amazon.com/s3/>`__ services. Understanding the
 fundamentals of these services will further enhance the developer
 experience with AWS F2 instances and the FPGA Developer Kit.
 
+.. _next-steps:
+
 Next Steps
 ----------
 
@@ -313,5 +329,5 @@ FPGA Development Kit:
   JTAG <./hdk/docs/Virtual_JTAG_XVC.html>`__ to run hardware debug.
 
 .. |f2_instances| image:: ./_static/instance_sizes.png
-.. |image1| image:: ./_static/accel_card_specs.png
+.. |image1| image:: ./_static/accel_card_specs_20250110.png
 .. |f2_f1_comp| image:: ./_static/f2_f1_comp.png
diff --git a/docs-rtd/source/_static/accel_card_specs.png b/docs-rtd/source/_static/accel_card_specs.png
diff --git a/docs-rtd/source/_static/accel_card_specs_20250110.png b/docs-rtd/source/_static/accel_card_specs_20250110.png
diff --git a/docs-rtd/source/_static/sdk/apps/virtual-ethernet/Virtual_Ethernet_Pktgen.jpg b/docs-rtd/source/_static/sdk/apps/virtual-ethernet/Virtual_Ethernet_Pktgen.jpg
diff --git a/docs-rtd/source/conf.py b/docs-rtd/source/conf.py
@@ -70,9 +70,9 @@
 # built documents.
 #
 # The short X.Y version.
-version = '0.1'
+version = '2.0'
 # The full version, including alpha/beta/rc tags.
-release = '0.1'
+release = '2.0'
 
 # The language for content autogenerated by Sphinx. Refer to documentation
 # for a list of supported languages.

diff --git a/docs-rtd/source/hdk/docs/AWS_Shell_ERRATA.rst b/docs-rtd/source/hdk/docs/AWS_Shell_ERRATA.rst
@@ -34,3 +34,19 @@ Unsupported Features
 
 Known Bugs/Issues
 -----------------
+
+- HBM ECC Scrubbing is not supported in Small Shell `0x10212415`:
+
+  - DO NOT enable the "Enable ECC Scrubbing" or the
+    "Initialize Memory Using ECC" option in the HBM IP. Enabling either option
+    will cause an HBM monitor interface timeout during AFI loading, making the
+    HBM inaccessible. Refer to `AWS Shell Interface Specification
+    <./AWS_Shell_Interface_Specification.html>`__ for details.
+
+  - ECC protection remains available. Developers can enable only the
+    "Enable ECC Correction" option in the IP configuration to use it.
+    **Note: Reading from uninitialized memory locations will result
+    in ECC errors**.
+
+  - Support for the "Enable ECC Scrubbing" and "Initialize Memory Using ECC"
+    options will be added in a future shell release.
diff --git a/docs-rtd/source/sdk/README.rst b/docs-rtd/source/sdk/README.rst
@@ -61,3 +61,19 @@ instance.
 
 Please reach out to the AWS FPGA team with any instability issues so we
 can help as soon as possible.
+
+Additional SDK Documentation
+----------------------------
+
+.. toctree::
+   :maxdepth: 1
+
+   apps/virtual-ethernet/README
+   apps/virtual-ethernet/doc/SDE_HW_Guide
+   apps/virtual-ethernet/doc/Virtual_Ethernet_Application_Guide
+
+   userspace/fpga_mgmt_examples/README
+
+   userspace/fpga_mgmt_tools/README
+
+`Back to Home <../index.html>`__
diff --git a/docs-rtd/source/sdk/apps/virtual-ethernet/README.rst b/docs-rtd/source/sdk/apps/virtual-ethernet/README.rst
@@ -36,7 +36,7 @@ processing, and runs mostly in Linux user-space.
 The following diagram shows the high level architecture for the Virtual
 Ethernet sample application(s) and Bringup/Debug tools.
 
-|alt tag|
+.. image:: ./../../../_static/sdk/apps/virtual-ethernet/Virtual_Ethernet_Arch.jpg
 
 User Space
 ----------

diff --git a/docs-rtd/source/sdk/apps/virtual-ethernet/doc/SDE_HW_Guide.rst b/docs-rtd/source/sdk/apps/virtual-ethernet/doc/SDE_HW_Guide.rst
@@ -76,7 +76,7 @@ Feature List
 Architecture
 ============
 
-|SDE_Block_Diagram|
+.. image:: ./../../../../_static/sdk/apps/virtual-ethernet/SDE_Block_Diagram.jpg
 
 The SDE uses shell's PCIM AXI4 interface to move packets between the AXI
 Streaming interface and the host. It implements a store and forward