Documentation hotfix

User_Guide_AWS_EC2_FPGA_Development_Kit.md

@@ -9,7 +9,7 @@ The development kit includes example designs to get you familiar with developing
     - [Comparison to F1](#comparison-to-f1)
   - [AWS EC2 F2 FPGA Development Kit](#aws-ec2-f2-fpga-development-kit)
     - [Development Environments](#development-environments)
-    - [Example Links](#example-links)
+    - [Quick Start Links](#quick-start-links)
     - [AWS Shells](#aws-shells)
     - [Hardware Development Kit (HDK)](#hardware-development-kit-hdk)
     - [Software-Defined Development Environment](#software-defined-development-environment)
@@ -49,19 +49,21 @@ This table lists the F2 development flows currently enabled and supported in the
 
 On-premise environment: Customers can set up a on-premise development environment using 2024.1 AMD tools with their own licenses. Refer to this guide [here](./hdk/docs/on_premise_licensing_help.md) for licensing requirements.
 
-### Example Links
+### Quick Start Links
 
 <!-- markdownlint-disable MD033 -->
 <table style="text-align: center">
   <tr>
     <th style="text-align: center">Development Environment</th>
     <th style="text-align: center">Example</th>
+    <th style="text-align: center">Description</th>
     <th style="text-align: center">Quick Start Guide</th>
     <th style="text-align: center">Resources</th>
   </tr>
   <tr>
     <td style="text-align: center" rowspan="12">HDK</td>
     <td style="text-align: center" rowspan="4"><a href="https://github.com/aws/aws-fpga/tree/f2/hdk/cl/examples/cl_mem_perf">cl_mem_perf</a></td>
+    <td style="text-align: center" rowspan="4">Demonstrates fine-tuned paths to memory to maximize bandwidth</td>
     <td style="text-align: center" rowspan="4"><a href="./hdk/README.md#build-accelerator-afi-using-hdk-design-flow">Guided Example</a></td>
     <td style="text-align: center"><a href="./hdk/cl/examples/cl_mem_perf/README.md">Design Spec</a></td>
   </tr>
@@ -76,6 +78,7 @@ On-premise environment: Customers can set up a on-premise development environmen
   </tr>
   <tr>
     <td style="text-align: center" rowspan="4"><a href="https://github.com/aws/aws-fpga/tree/f2/hdk/cl/examples/cl_dram_hbm_dma">cl_dram_hbm_dma</a></td>
+    <td style="text-align: center" rowspan="4">Demonstrates connectivity to various internal interfaces from the shell</td>
     <td style="text-align: center" rowspan="4"></td>
     <td style="text-align: center"><a href="./hdk/cl/examples/cl_dram_hbm_dma/README.md">Design Spec</a></td>
   </tr>
@@ -90,6 +93,7 @@ On-premise environment: Customers can set up a on-premise development environmen
   </tr>
   <tr>
     <td style="text-align: center" rowspan="4"><a href="https://github.com/aws/aws-fpga/tree/f2/hdk/cl/examples/cl_sde">cl_sde</a></td>
+    <td style="text-align: center" rowspan="4"><a href="https://github.com/aws/aws-fpga/blob/f2/sdk/apps/virtual-ethernet/">Demonstrates the use of the Streaming Data Engine (SDE) via the Virtual Ethernet Application</a></td>
     <td style="text-align: center" rowspan="4"></td>
     <td style="text-align: center"><a href="./hdk/cl/examples/cl_sde/README.md">Design Spec</a></td>
   </tr>
@@ -105,6 +109,7 @@ On-premise environment: Customers can set up a on-premise development environmen
   <tr>
     <td style="text-align: center" rowspan="4">Vitis</td>
     <td style="text-align: center" rowspan="4"><a href="https://github.com/Xilinx/Vitis_Accel_Examples/tree/2024.1/hello_world">hello_world</a></td>
+    <td style="text-align: center" rowspan="4">Demonstrates streaming to the FPGA rather than block transferring</td>
     <td style="text-align: center" rowspan="4"><a href="./vitis/README.md">Guided Example</td>
     <td style="text-align: center"><a href="https://github.com/Xilinx/Vitis_Accel_Examples/blob/main/hello_world/README.rst">Design Spec</a></td>
   </tr>

docs-rtd/Makefile

@@ -45,6 +45,7 @@ html:
 	$(SPHINXBUILD) -a -b html $(ALLSPHINXOPTS) $(BUILDDIR)/html
 	@echo
 	@echo "Build finished. The HTML pages are in $(BUILDDIR)/html."
+	cp source/google28e4accdfd74ffc3.html build/html
 
 dirhtml:
 	$(SPHINXBUILD) -b dirhtml $(ALLSPHINXOPTS) $(BUILDDIR)/dirhtml

docs-rtd/source/User-Guide-AWS-EC2-FPGA-Development-Kit.rst

@@ -17,7 +17,7 @@ developing for AWS EC2 FPGA Instances.
     Kit <#aws-ec2-f2-fpga-development-kit>`__
 
     - `Development Environments <#development-environments>`__
-    - `Example Links <#example-links>`__
+    - `Quick Start Links <#quick-start-links>`__
     - `AWS Shells <#aws-shells>`__
     - `Hardware Development Kit (HDK) <#hardware-development-kit-hdk>`__
     - `Software-Defined Development
@@ -134,80 +134,97 @@ environment using 2024.1 AMD tools with their own licenses. Refer to
 this guide `here <./hdk/docs/on-premise-licensing-help.html>`__ for
 licensing requirements.
 
-.. _example-links:
+.. _quick-start-links:
 
-Example Links
-~~~~~~~~~~~~~
+Quick Start Links
+~~~~~~~~~~~~~~~~~
 
 .. list-table::
    :header-rows: 1
-   :widths: 15 15 30 35
+   :widths: 15 15 30 15 25
 
    * - Development Environment
      - Example
+     - Description
      - Quick-Start Guide
      - Resources
    * - HDK
      - `cl_mem_perf <https://github.com/aws/aws-fpga/tree/f2/hdk/cl/examples/cl_mem_perf>`__
+     - Demonstrates fine-tuned paths to memory to maximize bandwidth
      - `Guided Example <./hdk/README.html#getting-started-hdk>`__
      - `Design Spec <./hdk/cl/examples/cl-mem-perf/README.html>`__
    * -
+     -
      -
      -
      - `Design Source Code <https://github.com/aws/aws-fpga/tree/f2/hdk/cl/examples/cl_mem_perf/design>`__
    * -
+     -
      -
      -
      - `Testbench <https://github.com/aws/aws-fpga/tree/f2/hdk/cl/examples/cl_mem_perf/verif>`__
    * -
+     -
      -
      -
      - `Runtime Software <https://github.com/aws/aws-fpga/tree/f2/hdk/cl/examples/cl_mem_perf/software>`__
    * -
      - `cl_dram_hbm_dma <https://github.com/aws/aws-fpga/tree/f2/hdk/cl/examples/cl_dram_hbm_dma>`__
+     - Demonstrates connectivity to various internal interfaces from the shell
      -
      - `Design Spec <./hdk/cl/examples/cl-dram-hbm-dma/README.html>`__
    * -
+     -
      -
      -
      - `Design Source Code <https://github.com/aws/aws-fpga/tree/f2/hdk/cl/examples/cl_dram_hbm_dma/design>`__
    * -
+     -
      -
      -
      - `Testbench <https://github.com/aws/aws-fpga/tree/f2/hdk/cl/examples/cl_dram_hbm_dma/verif>`__
    * -
+     -
      -
      -
      - `Runtime Software <https://github.com/aws/aws-fpga/tree/f2/hdk/cl/examples/cl_dram_hbm_dma/software>`__
    * -
      - `cl_sde <https://github.com/aws/aws-fpga/tree/f2/hdk/cl/examples/cl_sde>`__
+     - `Demonstrates the use of the Streaming Data Engine (SDE) via the Virtual Ethernet Application <https://github.com/aws/aws-fpga/tree/f2/sdk/apps/virtual-ethernet>`__
      -
      - `Design Spec <./hdk/cl/examples/cl-sde/README.html>`__
    * -
+     -
      -
      -
      - `Design Source Code <https://github.com/aws/aws-fpga/tree/f2/hdk/cl/examples/cl_sde/design>`__
    * -
+     -
      -
      -
      - `Testbench <https://github.com/aws/aws-fpga/tree/f2/hdk/cl/examples/cl_sde/verif>`__
    * -
+     -
      -
      -
      - `Runtime Software <https://github.com/aws/aws-fpga/tree/f2/hdk/cl/examples/cl_sde/software>`__
    * - Vitis
      - `hello_world <https://github.com/Xilinx/Vitis_Accel_Examples/tree/2024.1/hello_world>`__
+     - Demonstrates streaming data to the FPGA via the XRT
      - `Guided Example <./vitis/README.html>`__
      - `Design Spec <https://github.com/Xilinx/Vitis_Accel_Examples/blob/main/hello_world/README.rst>`__
    * -
+     -
      -
      -
      - `Design Source Code <https://github.com/Xilinx/Vitis_Accel_Examples/blob/main/hello_world/src/vadd.cpp>`__
    * -
+     -
      -
      -
      - `Testbench <https://github.com/Xilinx/Vitis_Accel_Examples/blob/main/hello_world/src/host.cpp#L92>`__
    * -
+     -
      -
      -
      - `Runtime Software <https://github.com/Xilinx/Vitis_Accel_Examples/blob/main/hello_world/src/host.cpp>`__

docs-rtd/source/_templates/layout.html

@@ -1,5 +1,5 @@
 {% extends "!layout.html" %}
 {% block extrahead %}
     {{ super() }}
-    <meta name="google-site-verification" content="8Towr1qSHYbKJeNUM4gRR3T13Rbh895fJjuafp8Hc10" />
-{% endblock %}
+    <meta name="google-site-verification" content="qIANNv1zFqrUiT3J8dIXZkUyaWrS_lLjtTk0tHTGRWw" />
+{% endblock %}