AGaMEMnon v0.5.0

AGaMEMnon v0.5.0

AGaMEMnon turns ordinary Verilog into an AG32 L48 fabric image with open tools only.
This release finds and removes the routing-table errors that made some default builds
produce silently wrong images, bounds every place-and-route attempt, fences one BRAM
mode that failed on silicon, and adds opt-in router-chosen LUT input pins. It is a
bounded L48 release, not vendor parity. See release validation
for the evidence behind each claim.

Tested on hardware

Results are from the release candidate on one AG32VF303CCT6 (L48) board, loaded into
SRAM, with a known-good reference image between designs.

Check	Result
Maintained corpus and holdouts, 18 fresh default builds	18/18 pass; 19/19 references
Stronger fast and slow RAM holdouts, 2 loads x 32 resets	64/64 and 64/64 (0/32 before this release)
Stronger FIFO and LFSR holdouts, 2 loads x 32 resets	61/64 and 61/64; see Known limitations
Designs that built wrong images during release preparation, rebuilt	pass
Router-chosen LUT inputs on, 38 designs	38/38 pass (38/38 with it off)

Software: the full Python suite and the native-toolchain complement pass with no
failures; installed wheels pass on Linux, Windows and macOS; the SDK archives build.

What changed

• Wrong routing-table rows are refused. Five default images that read back wrong
  on silicon were each traced on the board to one routing connection: rerouting only
  the net that used it made the image pass, and none was a timing effect (the first
  failed identically at 4, 10 and 40 MHz). All five take their selector codeword from
  a table that generalises codewords seen at one row or column to others, and the
  vendor's own bitgen has none of them. A vendor-bitgen check of every unconfirmed
  entry of that table found nine more, and six further connections select a different
  source than modelled. The flow refuses these 20 and retries around them; the device
  graph is unchanged. Evidence.
• Never-proven route shapes are refused. Routes through a source/destination pair
  and tile offset that no board-passing design has used are refused and retried (2,416
  pips, about 1% of fabric routing), as are 207 pips isolated by pass/fail board
  comparisons. Evidence.
• Every place-and-route attempt is bounded at 300 s. nextpnr's router2 could
  oscillate indefinitely; a timed-out attempt moves on to the next seed.
• x1 single-port BRAM writes need PORTA_OUTREG=1. The unregistered form failed on
  silicon while the registered form and the vendor image passed.
• A completed build is kept when an optional alternative reset mapping fails its
  bounded search.
• Opt-in router-chosen LUT inputs (AGAMEMNON_LUT_PIN_SWAP=1). The router may land
  a signal on any eligible input of a LUT and the truth table is permuted to match, as
  the vendor router does, with the vendor's freeze rules for feedback, register-bypass
  and carry inputs. Off, output is byte-identical to before.
• Earlier 0.5 changes (memory lowering, asynchronous clear, route retries, the PLL ratio
  model, BRAM source profiles, SDK packaging) are listed in the changelog.

Known limitations

• Synchronize external resets. A design that feeds an asynchronous input pin
  straight into a synchronous reset across many registers can start some registers a
  clock later than others. The stronger FIFO and LFSR holdouts do this and miss about
  3 in 64 reset releases; the same RTL with a two-flop reset synchronizer passed 96/96
  and 128/128. The vendor's images of the unsynchronized RTL pass, most likely because
  its reset routing has less skew; skew-aware reset routing is future work.
• Some dense designs refuse to build, for example with a forced --seed, when every
  legal route needs a refused connection. The build stops with a message instead of
  emitting an image.
• Router-chosen LUT inputs are opt-in. Their board A/B found no defect, but they
  change most images, including every byte-exact qualified fixture, so enabling them by
  default needs its own requalification.
• Build success is not silicon evidence. Test a new design on hardware.
• BRAM: x18 and x2 dual-port writes, x4 dual-port writes and read-only modes at X13Y4
  are the supported set. Timing is conservative and does not model clock skew. Other
  packages, the MCU AHB master and DMA, analog, and most hard-peripheral modes remain
  outside the tested scope. See supported scope and the
  roadmap.

Installation artifacts

The release workflow builds one wheel and embeds that exact wheel in the Windows
and Linux SDK archives. Each artifact has a SHA-256 sidecar:

agamemnon_ag32-0.5.0-py3-none-any.whl
agamemnon-sdk-linux-x64.tar.gz
agamemnon-sdk-windows-x64.zip

Verify the sidecars, activate the matching SDK environment, and check that
agamemnon --version reports agamemnon 0.5.0. A wheel alone does not install
all native FPGA/MCU tools. Follow installation and
agamemnon doctor --no-hardware for the required capabilities. The OpenOCD
transport remains a separate installation. Downloads are on the
release page.

AGaMEMnon v0.4.0

AGaMEMnon v0.4.0

AGaMEMnon v0.4.0 is an open, bounded toolchain release for the AG32 AGRV2K L48
envelope. It does not claim full vendor parity, universal timing, or correctness
for arbitrary RTL and placement.

Install

Download the six SDK release files from the v0.4.0 release page:

agamemnon_ag32-0.4.0-py3-none-any.whl
agamemnon_ag32-0.4.0-py3-none-any.whl.sha256
agamemnon-sdk-linux-x64.tar.gz
agamemnon-sdk-linux-x64.tar.gz.sha256
agamemnon-sdk-windows-x64.zip
agamemnon-sdk-windows-x64.zip.sha256

Verify the sidecars before installation. Extract the matching Linux or Windows
SDK archive, activate its environment (activate.sh or activate.ps1), and
check:

agamemnon --version

The result must be agamemnon 0.4.0. A wheel-only installation is also
available for inspection and offline verification:

python -m pip install agamemnon_ag32-0.4.0-py3-none-any.whl
agamemnon --version
agamemnon doctor --no-hardware

The SDK archives include the pinned OSS CAD Suite, RISC-V toolchain, AGRV2K
nextpnr build, runtime files where required, the wheel, and offline smoke
fixtures. The OpenOCD transport is distributed separately:

agamemnon install-openocd --version v0.1.0

Use the platform archive and matching checksum for Linux or Windows. The
published OpenOCD workflow covered four platform builds and its verification
gate; installation is still a transport capability and does not establish a
new silicon qualification.

Supported envelope

• Python inspection, project creation, offline verification, MCU compilation,
  and the bundled FPGA build flow are supported capabilities when their
  required host tools are available.
• Normal native builds use source-typed F/Q ownership for odd fabric sites.
  The installed regbank16 and util20 profiles reproduce their exact
  sampled hardware-tested raw and compressed images. This substantiates those
  bounded profiles; it does not qualify every odd-site composition.
• Exact retained AHB, carry, clock, physical-I/O, BRAM read-only, and selected
  BRAM write profiles remain available at their named part, package, route,
  frequency, and observable contract. Read the qualification records before
  treating any profile as a reusable design pattern.
• The ordinary placement density hint is --cap 16 for the documented
  publication examples. This is a hint for placement search, not a capacity
  guarantee and not a claim about every CLI default.
• --release-strict limits routing to the release-admitted routing policy. It is
  the tightest selector gate, but an accepted edge may be release-admitted by
  exact encoding evidence without a conduction witness at that position; it
  does not establish silicon correctness. Ordinary tiered routing remains
  evidence-tiered; research-unsafe routing is an explicit experiment mode and
  does not promote an image to release scope.

Limits and fences

The release retains 74 negative fences across 18 defect IDs. They prevent known
unsupported or silent-wrong images from being emitted. The fences remain part
of the safety boundary and are not failures of the release package.

Generic FSM and feedback behavior is not broadly qualified. Dense wide-state,
arbitrary BRAM write/dual-port, unqualified clock-region, broad peripheral,
bidirectional, alternate-package, electrical-margin, and AHB-master/DMA claims
remain outside the current qualification envelope. A successful decode, route,
CRC, or configuration acceptance does not establish silicon correctness. Timing
is qualified only for the named contracts and frequencies in the evidence
records.

The complete evidence, exact hashes, historical results, and terminal workflow
records are in RELEASE_VALIDATION_0_4_0.md
and the linked qualification records. See also STATUS.md and
INSTALLATION.md for current support and setup guidance.
Those records retain dated failed and cancelled runs without making them
current publication claims.

See the roadmap for the remaining correctness, capacity and
timing work beyond this release.

AGaMEMnon OpenOCD 0.1.0

Patched open-source OpenOCD for AG32 RISC-V debug through an ADIv5 DAP.

Includes Windows x64, Linux x64, macOS arm64 and macOS x64 binaries, matching SHA-256 files, and corresponding GPL source with patches and build instructions. The four builders produced the same normalized source archive.

Artifacts are the verified outputs of workflow 34088837146 at e913b09. OpenOCD source is pinned to patched commit f96d840a24e0c6694815293b803e18b535663c00. The Windows runtime matches the exact build that passed control-first installed public SRAM programming contracts on AG32/AGRV2K L48, including regbank16 and util20. Other platform builds passed their build/parser gates; this is not a claim of hardware qualification on every host or of general flash-programming qualification.

Install through agamemnon install-openocd. See the included BUILD.md and provenance/SBOM for dependencies, source identities and rebuilding. This dependency release is separate from the upcoming AGaMEMnon v0.4.0 toolchain release.

AGaMEMnon v0.3.0

Full Changelog: v0.2.0...v0.3.0

AGaMEMnon v0.2.0

Full Changelog: v0.1.1...v0.2.0