[codegen] Emit literal identifiers for numeric ids

[seldridge]

Change the FIRRTL serializer to use literal identifiers if any identifiers begin with a leading digit. This is a FIRRTL 3.0.0 feature that simplifies parsing.

This enables literal identifier emission anywhere. However, this code path is only reachable via MixedVec due to mangling of numeric names to add a leading underscore in all other circumstances. In the future, this commit will enable removing this restriction and switching to literal identifiers when this happens.

No changes are made to annotation targets. E.g., the literal identifier, "wire 42" in circuit "Foo" and module "Bar" is still referred to by a local target "~Foo|Bar>42". This is intentional (for now). Targets don't have parsing ambiguity like FIRRTL text and the name of this wire is still "42" not "42". It follows that the storage of this name in FIRRTL IR is not changed. This is the same way that this is handled in CIRCT.

Release Notes

Use FIRRTL 3.0.0 emission of literal identifiers when a Chisel name begins with a digit.

Notes

This PR is stacked on #3188 (and should be merged after it).

Example

import chisel3._
import chisel3.util.MixedVec
import circt.stage.ChiselStage

class `9000` extends RawModule {
  val `0` = IO(Input(MixedVec(Bool())))
  val `1` = IO(Output(MixedVec(Bool())))

  val `2` = Wire(MixedVec(Bool()))
  dontTouch(`2`(0))
  `2`(0) := `0`(0)

  `1` := `2`
}

println(ChiselStage.emitCHIRRTL(new `9000`))
println(ChiselStage.emitSystemVerilog(new `9000`))

With this commit, this will produce the following FIRRTL and Verilog:

FIRRTL version 3.0.0
circuit iw :%[[
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~iw|iw>_2"
  }
]]
  module iw :
    input _0 : { `0` : UInt<1>}
    output _1 : { `0` : UInt<1>}

    wire _2 : { `0` : UInt<1>}
    connect _2.`0`, _0.`0`
    connect _1, _2

module iw(
  input  _0_0,
  output _1_0
);

  wire _2_0 = _0_0;
  assign _1_0 = _2_0;
endmodule

With further changes that go beyond this PR< this should emit as:

FIRRTL version 3.0.0
circuit iw :%[[
  {
    "class":"firrtl.transforms.DontTouchAnnotation",
    "target":"~iw|iw>2"
  }
]]
  module iw :
    input `0` : { `0` : UInt<1>}
    output `1` : { `0` : UInt<1>}

    wire `2` : { `0` : UInt<1>}
    connect `2`.`0`, `0`.`0`
    connect `1`,`2`

[jackkoenig]

Generally LGTM but question about verification statements

[jackkoenig]

What about verification Statements? They have labels which are names in the sense that they can be annotated and they should correspond to labels in the Verilog.

[seldridge]

Good catch. I had considered this and thought it wasn't necessary. However, it is. I added a commit that makes these literal identifiers and adds checks that it works here: 9587c6c