Rocket cosim framework

flake.nix

@@ -22,6 +22,11 @@
           verilator cmake ninja
           python3 python3Packages.bootstrapped-pip
           pkgsCross.riscv64-embedded.buildPackages.gcc
+
+          libargs glog fmt zlib
+          gnused coreutils gnugrep which
+          parallel protobuf antlr4 numactl
+
           circt
 
           spike riscvTests

overlay.nix

@@ -1,4 +1,5 @@
-final: prev: {
+final: prev:
+let
   riscvTests = final.pkgsCross.riscv64-embedded.stdenv.mkDerivation rec {
     pname = "riscv-tests";
     version = "55bbcc8c06637a31cc01970881ba8072838a9121";
@@ -17,4 +18,50 @@ final: prev: {
     ];
     buildPhase = "make RISCV_PREFIX=riscv64-none-elf-";
   };
+
+  libspike = let
+      version = "1.1.0";
+      pname = "libspike";
+      cmakeConfig = ''
+        add_library(libspike STATIC IMPORTED GLOBAL)
+        set_target_properties(libspike PROPERTIES
+          IMPORTED_LOCATION "${placeholder "out"}/lib/libriscv.so")
+        target_include_directories(libspike INTERFACE
+          "${placeholder "out"}/include"
+          "${placeholder "out"}/include/riscv"
+          "${placeholder "out"}/include/fesvr"
+          "${placeholder "out"}/include/softfloat"
+        )
+      '';
+    in
+      final.stdenv.mkDerivation {
+        inherit version pname cmakeConfig;
+        enableParallelBuilding = true;
+        nativeBuildInputs = [ final.dtc ];
+        src = final.fetchFromGitHub {
+          owner = "riscv";
+          repo = "riscv-isa-sim";
+          rev = "ab3225a3ff687fda8b4180f9e4e0949a400d1247";
+          sha256 = "sha256-2cC2goTmxWnkTm3Tq08R8YkkuI2Fj8fRvpEPVZ5JvUI=";
+        };
+        configureFlags = [
+          "--enable-commitlog"
+        ];
+        installPhase = ''
+          runHook preInstall
+          mkdir -p $out/include/{riscv,fesvr,softfloat} $out/lib $out/lib/cmake/libspike
+          cp riscv/*.h $out/include/riscv
+          cp fesvr/*.h $out/include/fesvr
+          cp softfloat/*.h $out/include/softfloat
+          cp config.h $out/include
+          cp *.so $out/lib
+          echo "$cmakeConfig" > $out/lib/cmake/libspike/libspike-config.cmake
+          runHook postInstall
+        '';
+      };
+in
+{
+  inherit   libspike riscvTests;
+
+
 }

src/main/scala/tile/Interrupts.scala

@@ -1,10 +1,10 @@
 // See LICENSE.SiFive for license details.
 
-package freechips.rocketchip.tile
+package tile
 
 import Chisel._
 
-import org.chipsalliance.cde.config.Parameters
+import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.interrupts._
 import freechips.rocketchip.util._
@@ -32,29 +32,6 @@ trait SinksExternalInterrupts { this: BaseTile =>
   protected val intSinkNode = IntSinkNode(IntSinkPortSimple())
   intSinkNode := intXbar.intnode
 
-  def cpuDevice: Device
-  val intcDevice = new DeviceSnippet {
-    override def parent = Some(cpuDevice)
-    def describe(): Description = {
-      Description("interrupt-controller", Map(
-        "compatible"           -> "riscv,cpu-intc".asProperty,
-        "interrupt-controller" -> Nil,
-        "#interrupt-cells"     -> 1.asProperty))
-    }
-  }
-
-  ResourceBinding {
-    intSinkNode.edges.in.flatMap(_.source.sources).map { case s =>
-      for (i <- s.range.start until s.range.end) {
-       csrIntMap.lift(i).foreach { j =>
-          s.resources.foreach { r =>
-            r.bind(intcDevice, ResourceInt(j))
-          }
-        }
-      }
-    }
-  }
-
   // TODO: the order of the following two functions must match, and
   //         also match the order which things are connected to the
   //         per-tile crossbar in subsystem.HasTiles.connectInterrupts

src/main/scala/tile/RocketTile.scala

@@ -1,10 +1,10 @@
 // See LICENSE.SiFive for license details.
 // See LICENSE.Berkeley for license details.
 
-package freechips.rocketchip.tile
+package tile
 
 import Chisel._
-import org.chipsalliance.cde.config._
+import freechips.rocketchip.config._
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.interrupts._
@@ -36,11 +36,11 @@ case class RocketTileParams(
 }
 
 class RocketTile private(
-      val rocketParams: RocketTileParams,
-      crossing: ClockCrossingType,
-      lookup: LookupByHartIdImpl,
-      q: Parameters)
-    extends BaseTile(rocketParams, crossing, lookup, q)
+                          val rocketParams: RocketTileParams,
+                          crossing: ClockCrossingType,
+                          lookup: LookupByHartIdImpl,
+                          q: Parameters)
+  extends BaseTile(rocketParams, crossing, lookup, q)
     with SinksExternalInterrupts
     with SourcesExternalNotifications
     with HasLazyRoCC  // implies CanHaveSharedFPU with CanHavePTW with HasHellaCache
@@ -87,20 +87,7 @@ class RocketTile private(
   val itimProperty = frontend.icache.itimProperty.toSeq.flatMap(p => Map("sifive,itim" -> p))
 
   val beuProperty = bus_error_unit.map(d => Map(
-          "sifive,buserror" -> d.device.asProperty)).getOrElse(Nil)
-
-  val cpuDevice: SimpleDevice = new SimpleDevice("cpu", Seq("sifive,rocket0", "riscv")) {
-    override def parent = Some(ResourceAnchors.cpus)
-    override def describe(resources: ResourceBindings): Description = {
-      val Description(name, mapping) = super.describe(resources)
-      Description(name, mapping ++ cpuProperties ++ nextLevelCacheProperty
-                  ++ tileProperties ++ dtimProperty ++ itimProperty ++ beuProperty)
-    }
-  }
-
-  ResourceBinding {
-    Resource(cpuDevice, "reg").bind(ResourceAddress(staticIdForMetadataUseOnly))
-  }
+    "sifive,buserror" -> d.device.asProperty)).getOrElse(Nil)
 
   override lazy val module = new RocketTileModuleImp(this)
 
@@ -120,9 +107,9 @@ class RocketTile private(
 }
 
 class RocketTileModuleImp(outer: RocketTile) extends BaseTileModuleImp(outer)
-    with HasFpuOpt
-    with HasLazyRoCCModule
-    with HasICacheFrontendModule {
+  with HasFpuOpt
+  with HasLazyRoCCModule
+  with HasICacheFrontendModule {
   Annotated.params(this, outer.rocketParams)
 
   val core = Module(new Rocket(outer)(outer.p))
@@ -133,9 +120,9 @@ class RocketTileModuleImp(outer: RocketTile) extends BaseTileModuleImp(outer)
   // Report when the tile has ceased to retire instructions; for now the only cause is clock gating
   outer.reportCease(outer.rocketParams.core.clockGate.option(
     !outer.dcache.module.io.cpu.clock_enabled &&
-    !outer.frontend.module.io.cpu.clock_enabled &&
-    !ptw.io.dpath.clock_enabled &&
-    core.io.cease))
+      !outer.frontend.module.io.cpu.clock_enabled &&
+      !ptw.io.dpath.clock_enabled &&
+      core.io.cease))
 
   outer.reportWFI(Some(core.io.wfi))
 
@@ -182,8 +169,8 @@ class RocketTileModuleImp(outer: RocketTile) extends BaseTileModuleImp(outer)
   require(h == c, s"port list size was $h, core expected $c")
   require(h == o, s"port list size was $h, outer counted $o")
   // TODO figure out how to move the below into their respective mix-ins
-  dcacheArb.io.requestor <> dcachePorts.toSeq
-  ptw.io.requestor <> ptwPorts.toSeq
+  dcacheArb.io.requestor <> dcachePorts
+  ptw.io.requestor <> ptwPorts
 }
 
 trait HasFpuOpt { this: RocketTileModuleImp =>

tests/cases/entrance/entrance.S

@@ -0,0 +1,9 @@
+.global _start
+_start:
+    auipc t1, 0x0
+    addi a1, t1, 32
+    csrr a0, mhartid
+    lui t0, 0x80000
+    slli t0,t0,32
+    srli t0,t0,32
+    jr t0

tests/cases/smoketest/smoke.S

@@ -0,0 +1,19 @@
+.global _start
+_start:
+    add t0,t0,x0
+    addi t0, x0, 0x1
+    addi t1, x0, 0x0
+    addi t3, x0, 0xa
+loop:
+    add t1, t1, t0
+    add t0, t0, 0x1
+    add t3, t3, -1
+    bne t3, x0, loop
+    sd t1, 0x10(x0)
+    ld t2, 0x10(x0)
+    addi x20, x0, 0x1
+    addi x21, x0, 0x1
+    addi x22, x0, 0x1
+    addi x23, x0, 0x1
+    addi x24, x0, 0x1
+    addi x25, x0, 0x1

tests/cosim/elaborate/src/DUT.scala

@@ -0,0 +1,97 @@
+package cosim.elabotate
+
+import chisel3._
+import freechips.rocketchip.diplomacy.{AddressSet, BundleBridgeSource, InModuleBody, LazyModule, RegionType, SimpleLazyModule, TransferSizes}
+import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple, IntSourceNode, IntSourcePortSimple}
+import freechips.rocketchip.subsystem._
+import freechips.rocketchip.tilelink.{TLManagerNode, TLSlaveParameters, TLSlavePortParameters}
+import org.chipsalliance.cde.config.Parameters
+import freechips.rocketchip.tile.{NMI, PriorityMuxHartIdFromSeq, RocketTile}
+
+import org.chipsalliance.cde.config.{Config, Field}
+
+class DUT(p: Parameters) extends Module {
+  implicit val implicitP = p
+  val tileParams = p(RocketTileParamsKey)
+  val ldut = LazyModule(new SimpleLazyModule {
+    implicit val implicitP = p
+    val rocketTile = LazyModule(new RocketTile(tileParams, RocketCrossingParams(), PriorityMuxHartIdFromSeq(Seq(tileParams))))
+    val masterNode = TLManagerNode(Seq(TLSlavePortParameters.v1(
+      Seq(TLSlaveParameters.v1(
+        address = List(AddressSet(0x0, 0xffffffffL)),
+        regionType = RegionType.UNCACHED,
+        executable = true,
+        supportsGet = TransferSizes(1, 64),
+        supportsAcquireT = TransferSizes(1, 64),
+        supportsAcquireB = TransferSizes(1, 64),
+        supportsPutPartial = TransferSizes(1, 64),
+        supportsPutFull = TransferSizes(1, 64),
+        supportsLogical = TransferSizes(1, 64),
+        supportsArithmetic = TransferSizes(1, 64),
+        fifoId = Some(0))),
+      beatBytes = 8,
+      endSinkId = 4,
+      minLatency = 1
+    )))
+    masterNode :=* rocketTile.masterNode
+    val memory = InModuleBody {
+      masterNode.makeIOs()
+    }
+
+    val intNode = IntSourceNode(IntSourcePortSimple())
+    rocketTile.intInwardNode :=* intNode
+    val intIn = InModuleBody {
+      intNode.makeIOs()
+    }
+
+    val haltNode = IntSinkNode(IntSinkPortSimple())
+    haltNode :=* rocketTile.haltNode
+    val haltOut = InModuleBody {
+      haltNode.makeIOs()
+    }
+
+    val ceaseNode = IntSinkNode(IntSinkPortSimple())
+    ceaseNode :=* rocketTile.ceaseNode
+    val ceaseOut = InModuleBody {
+      ceaseNode.makeIOs()
+    }
+
+    val wfiNode = IntSinkNode(IntSinkPortSimple())
+    wfiNode :=* rocketTile.wfiNode
+    val wfiOut = InModuleBody {
+      wfiNode.makeIOs()
+    }
+    val resetVectorNode = BundleBridgeSource(() => UInt(32.W))
+    rocketTile.resetVectorNode := resetVectorNode
+    val resetVector = InModuleBody {
+      resetVectorNode.makeIO()
+    }
+    val hartidNode = BundleBridgeSource(() => UInt(4.W))
+    rocketTile.hartIdNode := hartidNode
+    InModuleBody {
+      hartidNode.bundle := 0.U
+    }
+    val nmiNode = BundleBridgeSource(Some(() => new NMI(32)))
+    rocketTile.nmiNode := nmiNode
+    val nmi = InModuleBody {
+      nmiNode.makeIO()
+    }
+  })
+  chisel3.experimental.DataMirror.fullModulePorts(
+    // instantiate the LazyModule
+    Module(ldut.module)
+  ).filterNot(_._2.isInstanceOf[Aggregate]).foreach { case (name, ele) =>
+    if (!(name == "clock" || name == "reset")) {
+      chisel3.experimental.DataMirror.directionOf(ele) match {
+        case ActualDirection.Output =>
+          val io = IO(Output(chiselTypeOf(ele))).suggestName(name)
+          println(s"output $name")
+          io := ele
+        case ActualDirection.Input =>
+          val io = IO(Input(chiselTypeOf(ele))).suggestName(name)
+          println(s"input $name")
+          ele := io
+      }
+    }
+  }
+}