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drm/i915/display: implement wa_18038517565
Disable FBC compressor clock gating before enabling FBC and clear it after disabling FBC. v2: update the DG2 registers for this wa v3: use local variable and single line reg definition (Jani) Bspec: 74212, 72197, 69741, 65555 Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Link: https://lore.kernel.org/r/20250330172616.718188-1-vinod.govindapillai@intel.com
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drivers/gpu/drm/i915/display/intel_fbc.c

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -520,6 +520,20 @@ static void ilk_fbc_activate(struct intel_fbc *fbc)
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DPFC_CTL_EN | g4x_dpfc_ctl(fbc));
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}
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static void fbc_compressor_clkgate_disable_wa(struct intel_fbc *fbc,
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bool disable)
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{
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struct intel_display *display = fbc->display;
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if (display->platform.dg2)
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intel_de_rmw(display, GEN9_CLKGATE_DIS_4, DG2_DPFC_GATING_DIS,
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disable ? DG2_DPFC_GATING_DIS : 0);
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else if (DISPLAY_VER(display) >= 14)
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intel_de_rmw(display, MTL_PIPE_CLKGATE_DIS2(fbc->id),
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MTL_DPFC_GATING_DIS,
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disable ? MTL_DPFC_GATING_DIS : 0);
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}
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static void ilk_fbc_deactivate(struct intel_fbc *fbc)
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{
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struct intel_display *display = fbc->display;
@@ -533,6 +547,10 @@ static void ilk_fbc_deactivate(struct intel_fbc *fbc)
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if (dpfc_ctl & DPFC_CTL_EN) {
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dpfc_ctl &= ~DPFC_CTL_EN;
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intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
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/* wa_18038517565 Enable DPFC clock gating after FBC disable */
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if (display->platform.dg2 || DISPLAY_VER(display) >= 14)
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fbc_compressor_clkgate_disable_wa(fbc, false);
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}
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}
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@@ -922,6 +940,10 @@ static void intel_fbc_program_workarounds(struct intel_fbc *fbc)
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if (DISPLAY_VER(display) >= 11 && !display->platform.dg2)
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intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id),
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0, DPFC_CHICKEN_FORCE_SLB_INVALIDATION);
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/* wa_18038517565 Disable DPFC clock gating before FBC enable */
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if (display->platform.dg2 || DISPLAY_VER(display) >= 14)
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fbc_compressor_clkgate_disable_wa(fbc, true);
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}
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static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)

drivers/gpu/drm/i915/i915_reg.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1077,6 +1077,7 @@
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#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
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#define BXT_GMBUS_GATING_DIS (1 << 14)
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#define DG2_DPFC_GATING_DIS REG_BIT(31)
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#define GEN9_CLKGATE_DIS_5 _MMIO(0x46540)
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#define DPCE_GATING_DIS REG_BIT(17)
@@ -4242,6 +4243,11 @@ enum skl_power_gate {
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#define MTL_CLKGATE_DIS_TRANS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _MTL_CLKGATE_DIS_TRANS_A)
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#define MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS REG_BIT(7)
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#define _MTL_PIPE_CLKGATE_DIS2_A 0x60114
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#define _MTL_PIPE_CLKGATE_DIS2_B 0x61114
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#define MTL_PIPE_CLKGATE_DIS2(pipe) _MMIO_PIPE(pipe, _MTL_PIPE_CLKGATE_DIS2_A, _MTL_PIPE_CLKGATE_DIS2_B)
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#define MTL_DPFC_GATING_DIS REG_BIT(6)
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#define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700)
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#define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8)
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#define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4)

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