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kuba-mookuba-moo
committed
Merge branch 'net-stmmac-yet-more-eee-updates'
Russell King says: ==================== net: stmmac: yet more EEE updates Continuing on with the STMMAC EEE cleanups from last cycle, this series further cleans up the EEE code, and fixes a problem with the existing implementation - disabling EEE doesn't immediately disable LPI signalling until the next packet is transmitted. It likely also fixes a potential race condition when trying to disable LPI vs the software timer. ==================== Link: https://patch.msgid.link/Z6NqGnM2yL7Ayo-T@shell.armlinux.org.uk Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2 parents be258f6 + 62b0a03 commit 02c9722

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9 files changed

+153
-224
lines changed

9 files changed

+153
-224
lines changed

‎drivers/net/ethernet/stmicro/stmmac/common.h‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -530,6 +530,20 @@ struct dma_features {
530530
#define STMMAC_DEFAULT_TWT_LS 0x1E
531531
#define STMMAC_ET_MAX 0xFFFFF
532532

533+
/* Common LPI register bits */
534+
#define LPI_CTRL_STATUS_LPITCSE BIT(21) /* LPI Tx Clock Stop Enable, gmac4, xgmac2 only */
535+
#define LPI_CTRL_STATUS_LPIATE BIT(20) /* LPI Timer Enable, gmac4 only */
536+
#define LPI_CTRL_STATUS_LPITXA BIT(19) /* Enable LPI TX Automate */
537+
#define LPI_CTRL_STATUS_PLSEN BIT(18) /* Enable PHY Link Status */
538+
#define LPI_CTRL_STATUS_PLS BIT(17) /* PHY Link Status */
539+
#define LPI_CTRL_STATUS_LPIEN BIT(16) /* LPI Enable */
540+
#define LPI_CTRL_STATUS_RLPIST BIT(9) /* Receive LPI state, gmac1000 only? */
541+
#define LPI_CTRL_STATUS_TLPIST BIT(8) /* Transmit LPI state, gmac1000 only? */
542+
#define LPI_CTRL_STATUS_RLPIEX BIT(3) /* Receive LPI Exit */
543+
#define LPI_CTRL_STATUS_RLPIEN BIT(2) /* Receive LPI Entry */
544+
#define LPI_CTRL_STATUS_TLPIEX BIT(1) /* Transmit LPI Exit */
545+
#define LPI_CTRL_STATUS_TLPIEN BIT(0) /* Transmit LPI Entry */
546+
533547
#define STMMAC_CHAIN_MODE 0x1
534548
#define STMMAC_RING_MODE 0x2
535549

‎drivers/net/ethernet/stmicro/stmmac/dwmac1000.h‎

Lines changed: 1 addition & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -59,22 +59,11 @@ enum power_event {
5959
/* Energy Efficient Ethernet (EEE)
6060
*
6161
* LPI status, timer and control register offset
62+
* For LPI control and status bit definitions, see common.h.
6263
*/
6364
#define LPI_CTRL_STATUS 0x0030
6465
#define LPI_TIMER_CTRL 0x0034
6566

66-
/* LPI control and status defines */
67-
#define LPI_CTRL_STATUS_LPITXA 0x00080000 /* Enable LPI TX Automate */
68-
#define LPI_CTRL_STATUS_PLSEN 0x00040000 /* Enable PHY Link Status */
69-
#define LPI_CTRL_STATUS_PLS 0x00020000 /* PHY Link Status */
70-
#define LPI_CTRL_STATUS_LPIEN 0x00010000 /* LPI Enable */
71-
#define LPI_CTRL_STATUS_RLPIST 0x00000200 /* Receive LPI state */
72-
#define LPI_CTRL_STATUS_TLPIST 0x00000100 /* Transmit LPI state */
73-
#define LPI_CTRL_STATUS_RLPIEX 0x00000008 /* Receive LPI Exit */
74-
#define LPI_CTRL_STATUS_RLPIEN 0x00000004 /* Receive LPI Entry */
75-
#define LPI_CTRL_STATUS_TLPIEX 0x00000002 /* Transmit LPI Exit */
76-
#define LPI_CTRL_STATUS_TLPIEN 0x00000001 /* Transmit LPI Entry */
77-
7867
/* GMAC HW ADDR regs */
7968
#define GMAC_ADDR_HIGH(reg) ((reg > 15) ? 0x00000800 + (reg - 16) * 8 : \
8069
0x00000040 + (reg * 8))

‎drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c‎

Lines changed: 11 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -342,31 +342,24 @@ static int dwmac1000_irq_status(struct mac_device_info *hw,
342342
return ret;
343343
}
344344

345-
static void dwmac1000_set_eee_mode(struct mac_device_info *hw,
346-
bool en_tx_lpi_clockgating)
345+
static int dwmac1000_set_lpi_mode(struct mac_device_info *hw,
346+
enum stmmac_lpi_mode mode,
347+
bool en_tx_lpi_clockgating, u32 et)
347348
{
348349
void __iomem *ioaddr = hw->pcsr;
349350
u32 value;
350351

351-
/*TODO - en_tx_lpi_clockgating treatment */
352+
if (mode == STMMAC_LPI_TIMER)
353+
return -EOPNOTSUPP;
352354

353-
/* Enable the link status receive on RGMII, SGMII ore SMII
354-
* receive path and instruct the transmit to enter in LPI
355-
* state.
356-
*/
357355
value = readl(ioaddr + LPI_CTRL_STATUS);
358-
value |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA;
356+
if (mode == STMMAC_LPI_FORCED)
357+
value |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA;
358+
else
359+
value &= ~(LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA);
359360
writel(value, ioaddr + LPI_CTRL_STATUS);
360-
}
361-
362-
static void dwmac1000_reset_eee_mode(struct mac_device_info *hw)
363-
{
364-
void __iomem *ioaddr = hw->pcsr;
365-
u32 value;
366361

367-
value = readl(ioaddr + LPI_CTRL_STATUS);
368-
value &= ~(LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA);
369-
writel(value, ioaddr + LPI_CTRL_STATUS);
362+
return 0;
370363
}
371364

372365
static void dwmac1000_set_eee_pls(struct mac_device_info *hw, int link)
@@ -509,8 +502,7 @@ const struct stmmac_ops dwmac1000_ops = {
509502
.pmt = dwmac1000_pmt,
510503
.set_umac_addr = dwmac1000_set_umac_addr,
511504
.get_umac_addr = dwmac1000_get_umac_addr,
512-
.set_eee_mode = dwmac1000_set_eee_mode,
513-
.reset_eee_mode = dwmac1000_reset_eee_mode,
505+
.set_lpi_mode = dwmac1000_set_lpi_mode,
514506
.set_eee_timer = dwmac1000_set_eee_timer,
515507
.set_eee_pls = dwmac1000_set_eee_pls,
516508
.debug = dwmac1000_debug,

‎drivers/net/ethernet/stmicro/stmmac/dwmac4.h‎

Lines changed: 1 addition & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -177,23 +177,13 @@ enum power_event {
177177
/* Energy Efficient Ethernet (EEE) for GMAC4
178178
*
179179
* LPI status, timer and control register offset
180+
* For LPI control and status bit definitions, see common.h.
180181
*/
181182
#define GMAC4_LPI_CTRL_STATUS 0xd0
182183
#define GMAC4_LPI_TIMER_CTRL 0xd4
183184
#define GMAC4_LPI_ENTRY_TIMER 0xd8
184185
#define GMAC4_MAC_ONEUS_TIC_COUNTER 0xdc
185186

186-
/* LPI control and status defines */
187-
#define GMAC4_LPI_CTRL_STATUS_LPITCSE BIT(21) /* LPI Tx Clock Stop Enable */
188-
#define GMAC4_LPI_CTRL_STATUS_LPIATE BIT(20) /* LPI Timer Enable */
189-
#define GMAC4_LPI_CTRL_STATUS_LPITXA BIT(19) /* Enable LPI TX Automate */
190-
#define GMAC4_LPI_CTRL_STATUS_PLS BIT(17) /* PHY Link Status */
191-
#define GMAC4_LPI_CTRL_STATUS_LPIEN BIT(16) /* LPI Enable */
192-
#define GMAC4_LPI_CTRL_STATUS_RLPIEX BIT(3) /* Receive LPI Exit */
193-
#define GMAC4_LPI_CTRL_STATUS_RLPIEN BIT(2) /* Receive LPI Entry */
194-
#define GMAC4_LPI_CTRL_STATUS_TLPIEX BIT(1) /* Transmit LPI Exit */
195-
#define GMAC4_LPI_CTRL_STATUS_TLPIEN BIT(0) /* Transmit LPI Entry */
196-
197187
/* MAC Debug bitmap */
198188
#define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17)
199189
#define GMAC_DEBUG_TFCSTS_SHIFT 17

‎drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c‎

Lines changed: 41 additions & 55 deletions
Original file line numberDiff line numberDiff line change
@@ -376,33 +376,46 @@ static void dwmac4_get_umac_addr(struct mac_device_info *hw,
376376
GMAC_ADDR_LOW(reg_n));
377377
}
378378

379-
static void dwmac4_set_eee_mode(struct mac_device_info *hw,
380-
bool en_tx_lpi_clockgating)
379+
static int dwmac4_set_lpi_mode(struct mac_device_info *hw,
380+
enum stmmac_lpi_mode mode,
381+
bool en_tx_lpi_clockgating, u32 et)
381382
{
382383
void __iomem *ioaddr = hw->pcsr;
383-
u32 value;
384+
u32 value, mask;
384385

385-
/* Enable the link status receive on RGMII, SGMII ore SMII
386-
* receive path and instruct the transmit to enter in LPI
387-
* state.
388-
*/
389-
value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
390-
value |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
386+
if (mode == STMMAC_LPI_DISABLE) {
387+
value = 0;
388+
} else {
389+
value = LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA;
391390

392-
if (en_tx_lpi_clockgating)
393-
value |= GMAC4_LPI_CTRL_STATUS_LPITCSE;
391+
if (mode == STMMAC_LPI_TIMER) {
392+
/* Return ERANGE if the timer is larger than the
393+
* register field.
394+
*/
395+
if (et > STMMAC_ET_MAX)
396+
return -ERANGE;
394397

395-
writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
396-
}
398+
/* Set the hardware LPI entry timer */
399+
writel(et, ioaddr + GMAC4_LPI_ENTRY_TIMER);
397400

398-
static void dwmac4_reset_eee_mode(struct mac_device_info *hw)
399-
{
400-
void __iomem *ioaddr = hw->pcsr;
401-
u32 value;
401+
/* Interpret a zero LPI entry timer to mean
402+
* immediate entry into LPI mode.
403+
*/
404+
if (et)
405+
value |= LPI_CTRL_STATUS_LPIATE;
406+
}
402407

403-
value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
404-
value &= ~(GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA);
408+
if (en_tx_lpi_clockgating)
409+
value |= LPI_CTRL_STATUS_LPITCSE;
410+
}
411+
412+
mask = LPI_CTRL_STATUS_LPIATE | LPI_CTRL_STATUS_LPIEN |
413+
LPI_CTRL_STATUS_LPITXA | LPI_CTRL_STATUS_LPITCSE;
414+
415+
value |= readl(ioaddr + GMAC4_LPI_CTRL_STATUS) & ~mask;
405416
writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
417+
418+
return 0;
406419
}
407420

408421
static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)
@@ -413,34 +426,13 @@ static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)
413426
value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
414427

415428
if (link)
416-
value |= GMAC4_LPI_CTRL_STATUS_PLS;
429+
value |= LPI_CTRL_STATUS_PLS;
417430
else
418-
value &= ~GMAC4_LPI_CTRL_STATUS_PLS;
431+
value &= ~LPI_CTRL_STATUS_PLS;
419432

420433
writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
421434
}
422435

423-
static void dwmac4_set_eee_lpi_entry_timer(struct mac_device_info *hw, u32 et)
424-
{
425-
void __iomem *ioaddr = hw->pcsr;
426-
u32 value = et & STMMAC_ET_MAX;
427-
int regval;
428-
429-
/* Program LPI entry timer value into register */
430-
writel(value, ioaddr + GMAC4_LPI_ENTRY_TIMER);
431-
432-
/* Enable/disable LPI entry timer */
433-
regval = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
434-
regval |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
435-
436-
if (et)
437-
regval |= GMAC4_LPI_CTRL_STATUS_LPIATE;
438-
else
439-
regval &= ~GMAC4_LPI_CTRL_STATUS_LPIATE;
440-
441-
writel(regval, ioaddr + GMAC4_LPI_CTRL_STATUS);
442-
}
443-
444436
static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
445437
{
446438
void __iomem *ioaddr = hw->pcsr;
@@ -849,17 +841,17 @@ static int dwmac4_irq_status(struct mac_device_info *hw,
849841
/* Clear LPI interrupt by reading MAC_LPI_Control_Status */
850842
u32 status = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
851843

852-
if (status & GMAC4_LPI_CTRL_STATUS_TLPIEN) {
844+
if (status & LPI_CTRL_STATUS_TLPIEN) {
853845
ret |= CORE_IRQ_TX_PATH_IN_LPI_MODE;
854846
x->irq_tx_path_in_lpi_mode_n++;
855847
}
856-
if (status & GMAC4_LPI_CTRL_STATUS_TLPIEX) {
848+
if (status & LPI_CTRL_STATUS_TLPIEX) {
857849
ret |= CORE_IRQ_TX_PATH_EXIT_LPI_MODE;
858850
x->irq_tx_path_exit_lpi_mode_n++;
859851
}
860-
if (status & GMAC4_LPI_CTRL_STATUS_RLPIEN)
852+
if (status & LPI_CTRL_STATUS_RLPIEN)
861853
x->irq_rx_path_in_lpi_mode_n++;
862-
if (status & GMAC4_LPI_CTRL_STATUS_RLPIEX)
854+
if (status & LPI_CTRL_STATUS_RLPIEX)
863855
x->irq_rx_path_exit_lpi_mode_n++;
864856
}
865857

@@ -1201,9 +1193,7 @@ const struct stmmac_ops dwmac4_ops = {
12011193
.pmt = dwmac4_pmt,
12021194
.set_umac_addr = dwmac4_set_umac_addr,
12031195
.get_umac_addr = dwmac4_get_umac_addr,
1204-
.set_eee_mode = dwmac4_set_eee_mode,
1205-
.reset_eee_mode = dwmac4_reset_eee_mode,
1206-
.set_eee_lpi_entry_timer = dwmac4_set_eee_lpi_entry_timer,
1196+
.set_lpi_mode = dwmac4_set_lpi_mode,
12071197
.set_eee_timer = dwmac4_set_eee_timer,
12081198
.set_eee_pls = dwmac4_set_eee_pls,
12091199
.pcs_ctrl_ane = dwmac4_ctrl_ane,
@@ -1245,9 +1235,7 @@ const struct stmmac_ops dwmac410_ops = {
12451235
.pmt = dwmac4_pmt,
12461236
.set_umac_addr = dwmac4_set_umac_addr,
12471237
.get_umac_addr = dwmac4_get_umac_addr,
1248-
.set_eee_mode = dwmac4_set_eee_mode,
1249-
.reset_eee_mode = dwmac4_reset_eee_mode,
1250-
.set_eee_lpi_entry_timer = dwmac4_set_eee_lpi_entry_timer,
1238+
.set_lpi_mode = dwmac4_set_lpi_mode,
12511239
.set_eee_timer = dwmac4_set_eee_timer,
12521240
.set_eee_pls = dwmac4_set_eee_pls,
12531241
.pcs_ctrl_ane = dwmac4_ctrl_ane,
@@ -1291,9 +1279,7 @@ const struct stmmac_ops dwmac510_ops = {
12911279
.pmt = dwmac4_pmt,
12921280
.set_umac_addr = dwmac4_set_umac_addr,
12931281
.get_umac_addr = dwmac4_get_umac_addr,
1294-
.set_eee_mode = dwmac4_set_eee_mode,
1295-
.reset_eee_mode = dwmac4_reset_eee_mode,
1296-
.set_eee_lpi_entry_timer = dwmac4_set_eee_lpi_entry_timer,
1282+
.set_lpi_mode = dwmac4_set_lpi_mode,
12971283
.set_eee_timer = dwmac4_set_eee_timer,
12981284
.set_eee_pls = dwmac4_set_eee_pls,
12991285
.pcs_ctrl_ane = dwmac4_ctrl_ane,

‎drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h‎

Lines changed: 1 addition & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -112,14 +112,7 @@
112112
#define XGMAC_MGKPKTEN BIT(1)
113113
#define XGMAC_PWRDWN BIT(0)
114114
#define XGMAC_LPI_CTRL 0x000000d0
115-
#define XGMAC_TXCGE BIT(21)
116-
#define XGMAC_LPITXA BIT(19)
117-
#define XGMAC_PLS BIT(17)
118-
#define XGMAC_LPITXEN BIT(16)
119-
#define XGMAC_RLPIEX BIT(3)
120-
#define XGMAC_RLPIEN BIT(2)
121-
#define XGMAC_TLPIEX BIT(1)
122-
#define XGMAC_TLPIEN BIT(0)
115+
/* For definitions, see LPI_CTRL_STATUS_xxx in common.h */
123116
#define XGMAC_LPI_TIMER_CTRL 0x000000d4
124117
#define XGMAC_HW_FEATURE0 0x0000011c
125118
#define XGMAC_HWFEAT_EDMA BIT(31)

‎drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c‎

Lines changed: 23 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -316,17 +316,17 @@ static int dwxgmac2_host_irq_status(struct mac_device_info *hw,
316316
if (stat & XGMAC_LPIIS) {
317317
u32 lpi = readl(ioaddr + XGMAC_LPI_CTRL);
318318

319-
if (lpi & XGMAC_TLPIEN) {
319+
if (lpi & LPI_CTRL_STATUS_TLPIEN) {
320320
ret |= CORE_IRQ_TX_PATH_IN_LPI_MODE;
321321
x->irq_tx_path_in_lpi_mode_n++;
322322
}
323-
if (lpi & XGMAC_TLPIEX) {
323+
if (lpi & LPI_CTRL_STATUS_TLPIEX) {
324324
ret |= CORE_IRQ_TX_PATH_EXIT_LPI_MODE;
325325
x->irq_tx_path_exit_lpi_mode_n++;
326326
}
327-
if (lpi & XGMAC_RLPIEN)
327+
if (lpi & LPI_CTRL_STATUS_RLPIEN)
328328
x->irq_rx_path_in_lpi_mode_n++;
329-
if (lpi & XGMAC_RLPIEX)
329+
if (lpi & LPI_CTRL_STATUS_RLPIEX)
330330
x->irq_rx_path_exit_lpi_mode_n++;
331331
}
332332

@@ -425,29 +425,28 @@ static void dwxgmac2_get_umac_addr(struct mac_device_info *hw,
425425
addr[5] = (hi_addr >> 8) & 0xff;
426426
}
427427

428-
static void dwxgmac2_set_eee_mode(struct mac_device_info *hw,
429-
bool en_tx_lpi_clockgating)
428+
static int dwxgmac2_set_lpi_mode(struct mac_device_info *hw,
429+
enum stmmac_lpi_mode mode,
430+
bool en_tx_lpi_clockgating, u32 et)
430431
{
431432
void __iomem *ioaddr = hw->pcsr;
432433
u32 value;
433434

434-
value = readl(ioaddr + XGMAC_LPI_CTRL);
435-
436-
value |= XGMAC_LPITXEN | XGMAC_LPITXA;
437-
if (en_tx_lpi_clockgating)
438-
value |= XGMAC_TXCGE;
439-
440-
writel(value, ioaddr + XGMAC_LPI_CTRL);
441-
}
442-
443-
static void dwxgmac2_reset_eee_mode(struct mac_device_info *hw)
444-
{
445-
void __iomem *ioaddr = hw->pcsr;
446-
u32 value;
435+
if (mode == STMMAC_LPI_TIMER)
436+
return -EOPNOTSUPP;
447437

448438
value = readl(ioaddr + XGMAC_LPI_CTRL);
449-
value &= ~(XGMAC_LPITXEN | XGMAC_LPITXA | XGMAC_TXCGE);
439+
if (mode == STMMAC_LPI_FORCED) {
440+
value |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA;
441+
if (en_tx_lpi_clockgating)
442+
value |= LPI_CTRL_STATUS_LPITCSE;
443+
} else {
444+
value &= ~(LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA |
445+
LPI_CTRL_STATUS_LPITCSE);
446+
}
450447
writel(value, ioaddr + XGMAC_LPI_CTRL);
448+
449+
return 0;
451450
}
452451

453452
static void dwxgmac2_set_eee_pls(struct mac_device_info *hw, int link)
@@ -457,9 +456,9 @@ static void dwxgmac2_set_eee_pls(struct mac_device_info *hw, int link)
457456

458457
value = readl(ioaddr + XGMAC_LPI_CTRL);
459458
if (link)
460-
value |= XGMAC_PLS;
459+
value |= LPI_CTRL_STATUS_PLS;
461460
else
462-
value &= ~XGMAC_PLS;
461+
value &= ~LPI_CTRL_STATUS_PLS;
463462
writel(value, ioaddr + XGMAC_LPI_CTRL);
464463
}
465464

@@ -1525,8 +1524,7 @@ const struct stmmac_ops dwxgmac210_ops = {
15251524
.pmt = dwxgmac2_pmt,
15261525
.set_umac_addr = dwxgmac2_set_umac_addr,
15271526
.get_umac_addr = dwxgmac2_get_umac_addr,
1528-
.set_eee_mode = dwxgmac2_set_eee_mode,
1529-
.reset_eee_mode = dwxgmac2_reset_eee_mode,
1527+
.set_lpi_mode = dwxgmac2_set_lpi_mode,
15301528
.set_eee_timer = dwxgmac2_set_eee_timer,
15311529
.set_eee_pls = dwxgmac2_set_eee_pls,
15321530
.debug = NULL,
@@ -1582,8 +1580,7 @@ const struct stmmac_ops dwxlgmac2_ops = {
15821580
.pmt = dwxgmac2_pmt,
15831581
.set_umac_addr = dwxgmac2_set_umac_addr,
15841582
.get_umac_addr = dwxgmac2_get_umac_addr,
1585-
.set_eee_mode = dwxgmac2_set_eee_mode,
1586-
.reset_eee_mode = dwxgmac2_reset_eee_mode,
1583+
.set_lpi_mode = dwxgmac2_set_lpi_mode,
15871584
.set_eee_timer = dwxgmac2_set_eee_timer,
15881585
.set_eee_pls = dwxgmac2_set_eee_pls,
15891586
.debug = NULL,

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