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Michael ChanPaolo Abeni
Michael Chan
authored and
Paolo Abeni
committed
bnxt_en: Update firmware interface to 1.10.3.97
The main changes are adding i2c write for module eeprom and a new v2 PCIe statistics structure. Signed-off-by: Michael Chan <michael.chan@broadcom.com> Link: https://patch.msgid.link/20250310183129.3154117-6-michael.chan@broadcom.com Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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‎drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h‎

Lines changed: 119 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
*
33
* Copyright (c) 2014-2016 Broadcom Corporation
44
* Copyright (c) 2014-2018 Broadcom Limited
5-
* Copyright (c) 2018-2024 Broadcom Inc.
5+
* Copyright (c) 2018-2025 Broadcom Inc.
66
*
77
* This program is free software; you can redistribute it and/or modify
88
* it under the terms of the GNU General Public License as published by
@@ -438,6 +438,7 @@ struct cmd_nums {
438438
#define HWRM_MFG_PRVSN_EXPORT_CERT 0x219UL
439439
#define HWRM_STAT_DB_ERROR_QSTATS 0x21aUL
440440
#define HWRM_MFG_TESTS 0x21bUL
441+
#define HWRM_MFG_WRITE_CERT_NVM 0x21cUL
441442
#define HWRM_PORT_POE_CFG 0x230UL
442443
#define HWRM_PORT_POE_QCFG 0x231UL
443444
#define HWRM_UDCC_QCAPS 0x258UL
@@ -514,6 +515,8 @@ struct cmd_nums {
514515
#define HWRM_TFC_TBL_SCOPE_CONFIG_GET 0x39aUL
515516
#define HWRM_TFC_RESC_USAGE_QUERY 0x39bUL
516517
#define HWRM_TFC_GLOBAL_ID_FREE 0x39cUL
518+
#define HWRM_TFC_TCAM_PRI_UPDATE 0x39dUL
519+
#define HWRM_TFC_HOT_UPGRADE_PROCESS 0x3a0UL
517520
#define HWRM_SV 0x400UL
518521
#define HWRM_DBG_SERDES_TEST 0xff0eUL
519522
#define HWRM_DBG_LOG_BUFFER_FLUSH 0xff0fUL
@@ -629,8 +632,8 @@ struct hwrm_err_output {
629632
#define HWRM_VERSION_MAJOR 1
630633
#define HWRM_VERSION_MINOR 10
631634
#define HWRM_VERSION_UPDATE 3
632-
#define HWRM_VERSION_RSVD 85
633-
#define HWRM_VERSION_STR "1.10.3.85"
635+
#define HWRM_VERSION_RSVD 97
636+
#define HWRM_VERSION_STR "1.10.3.97"
634637

635638
/* hwrm_ver_get_input (size:192b/24B) */
636639
struct hwrm_ver_get_input {
@@ -1905,11 +1908,15 @@ struct hwrm_func_qcaps_output {
19051908
__le32 roce_vf_max_srq;
19061909
__le32 roce_vf_max_gid;
19071910
__le32 flags_ext3;
1908-
#define FUNC_QCAPS_RESP_FLAGS_EXT3_RM_RSV_WHILE_ALLOC_CAP 0x1UL
1909-
#define FUNC_QCAPS_RESP_FLAGS_EXT3_REQUIRE_L2_FILTER 0x2UL
1910-
#define FUNC_QCAPS_RESP_FLAGS_EXT3_MAX_ROCE_VFS_SUPPORTED 0x4UL
1911+
#define FUNC_QCAPS_RESP_FLAGS_EXT3_RM_RSV_WHILE_ALLOC_CAP 0x1UL
1912+
#define FUNC_QCAPS_RESP_FLAGS_EXT3_REQUIRE_L2_FILTER 0x2UL
1913+
#define FUNC_QCAPS_RESP_FLAGS_EXT3_MAX_ROCE_VFS_SUPPORTED 0x4UL
1914+
#define FUNC_QCAPS_RESP_FLAGS_EXT3_RX_RATE_PROFILE_SEL_SUPPORTED 0x8UL
1915+
#define FUNC_QCAPS_RESP_FLAGS_EXT3_BIDI_OPT_SUPPORTED 0x10UL
1916+
#define FUNC_QCAPS_RESP_FLAGS_EXT3_MIRROR_ON_ROCE_SUPPORTED 0x20UL
19111917
__le16 max_roce_vfs;
1912-
u8 unused_3[5];
1918+
__le16 max_crypto_rx_flow_filters;
1919+
u8 unused_3[3];
19131920
u8 valid;
19141921
};
19151922

@@ -1924,7 +1931,7 @@ struct hwrm_func_qcfg_input {
19241931
u8 unused_0[6];
19251932
};
19261933

1927-
/* hwrm_func_qcfg_output (size:1280b/160B) */
1934+
/* hwrm_func_qcfg_output (size:1344b/168B) */
19281935
struct hwrm_func_qcfg_output {
19291936
__le16 error_code;
19301937
__le16 req_type;
@@ -2087,14 +2094,18 @@ struct hwrm_func_qcfg_output {
20872094
__le16 host_mtu;
20882095
__le16 flags2;
20892096
#define FUNC_QCFG_RESP_FLAGS2_SRIOV_DSCP_INSERT_ENABLED 0x1UL
2090-
u8 unused_4[2];
2097+
__le16 stag_vid;
20912098
u8 port_kdnet_mode;
20922099
#define FUNC_QCFG_RESP_PORT_KDNET_MODE_DISABLED 0x0UL
20932100
#define FUNC_QCFG_RESP_PORT_KDNET_MODE_ENABLED 0x1UL
20942101
#define FUNC_QCFG_RESP_PORT_KDNET_MODE_LAST FUNC_QCFG_RESP_PORT_KDNET_MODE_ENABLED
20952102
u8 kdnet_pcie_function;
20962103
__le16 port_kdnet_fid;
2097-
u8 unused_5[2];
2104+
u8 unused_5;
2105+
u8 roce_bidi_opt_mode;
2106+
#define FUNC_QCFG_RESP_ROCE_BIDI_OPT_MODE_DISABLED 0x1UL
2107+
#define FUNC_QCFG_RESP_ROCE_BIDI_OPT_MODE_DEDICATED 0x2UL
2108+
#define FUNC_QCFG_RESP_ROCE_BIDI_OPT_MODE_SHARED 0x4UL
20982109
__le32 num_ktls_tx_key_ctxs;
20992110
__le32 num_ktls_rx_key_ctxs;
21002111
u8 lag_id;
@@ -2112,7 +2123,8 @@ struct hwrm_func_qcfg_output {
21122123
__le16 xid_partition_cfg;
21132124
#define FUNC_QCFG_RESP_XID_PARTITION_CFG_TX_CK 0x1UL
21142125
#define FUNC_QCFG_RESP_XID_PARTITION_CFG_RX_CK 0x2UL
2115-
u8 unused_7;
2126+
__le16 mirror_vnic_id;
2127+
u8 unused_7[7];
21162128
u8 valid;
21172129
};
21182130

@@ -3965,7 +3977,7 @@ struct ts_split_entries {
39653977
__le32 region_num_entries;
39663978
u8 tsid;
39673979
u8 lkup_static_bkt_cnt_exp[2];
3968-
u8 rsvd;
3980+
u8 locked;
39693981
__le32 rsvd2[2];
39703982
};
39713983

@@ -5483,6 +5495,37 @@ struct hwrm_port_phy_qcaps_output {
54835495
u8 valid;
54845496
};
54855497

5498+
/* hwrm_port_phy_i2c_write_input (size:832b/104B) */
5499+
struct hwrm_port_phy_i2c_write_input {
5500+
__le16 req_type;
5501+
__le16 cmpl_ring;
5502+
__le16 seq_id;
5503+
__le16 target_id;
5504+
__le64 resp_addr;
5505+
__le32 flags;
5506+
__le32 enables;
5507+
#define PORT_PHY_I2C_WRITE_REQ_ENABLES_PAGE_OFFSET 0x1UL
5508+
#define PORT_PHY_I2C_WRITE_REQ_ENABLES_BANK_NUMBER 0x2UL
5509+
__le16 port_id;
5510+
u8 i2c_slave_addr;
5511+
u8 bank_number;
5512+
__le16 page_number;
5513+
__le16 page_offset;
5514+
u8 data_length;
5515+
u8 unused_1[7];
5516+
__le32 data[16];
5517+
};
5518+
5519+
/* hwrm_port_phy_i2c_write_output (size:128b/16B) */
5520+
struct hwrm_port_phy_i2c_write_output {
5521+
__le16 error_code;
5522+
__le16 req_type;
5523+
__le16 seq_id;
5524+
__le16 resp_len;
5525+
u8 unused_0[7];
5526+
u8 valid;
5527+
};
5528+
54865529
/* hwrm_port_phy_i2c_read_input (size:320b/40B) */
54875530
struct hwrm_port_phy_i2c_read_input {
54885531
__le16 req_type;
@@ -6610,8 +6653,9 @@ struct hwrm_vnic_alloc_input {
66106653
__le32 flags;
66116654
#define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL
66126655
#define VNIC_ALLOC_REQ_FLAGS_VIRTIO_NET_FID_VALID 0x2UL
6656+
#define VNIC_ALLOC_REQ_FLAGS_VNIC_ID_VALID 0x4UL
66136657
__le16 virtio_net_fid;
6614-
u8 unused_0[2];
6658+
__le16 vnic_id;
66156659
};
66166660

66176661
/* hwrm_vnic_alloc_output (size:128b/16B) */
@@ -6710,6 +6754,7 @@ struct hwrm_vnic_cfg_input {
67106754
#define VNIC_CFG_REQ_ENABLES_QUEUE_ID 0x80UL
67116755
#define VNIC_CFG_REQ_ENABLES_RX_CSUM_V2_MODE 0x100UL
67126756
#define VNIC_CFG_REQ_ENABLES_L2_CQE_MODE 0x200UL
6757+
#define VNIC_CFG_REQ_ENABLES_RAW_QP_ID 0x400UL
67136758
__le16 vnic_id;
67146759
__le16 dflt_ring_grp;
67156760
__le16 rss_rule;
@@ -6729,7 +6774,7 @@ struct hwrm_vnic_cfg_input {
67296774
#define VNIC_CFG_REQ_L2_CQE_MODE_COMPRESSED 0x1UL
67306775
#define VNIC_CFG_REQ_L2_CQE_MODE_MIXED 0x2UL
67316776
#define VNIC_CFG_REQ_L2_CQE_MODE_LAST VNIC_CFG_REQ_L2_CQE_MODE_MIXED
6732-
u8 unused0[4];
6777+
__le32 raw_qp_id;
67336778
};
67346779

67356780
/* hwrm_vnic_cfg_output (size:128b/16B) */
@@ -7082,6 +7127,15 @@ struct hwrm_vnic_plcmodes_cfg_output {
70827127
u8 valid;
70837128
};
70847129

7130+
/* hwrm_vnic_plcmodes_cfg_cmd_err (size:64b/8B) */
7131+
struct hwrm_vnic_plcmodes_cfg_cmd_err {
7132+
u8 code;
7133+
#define VNIC_PLCMODES_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL
7134+
#define VNIC_PLCMODES_CFG_CMD_ERR_CODE_INVALID_HDS_THRESHOLD 0x1UL
7135+
#define VNIC_PLCMODES_CFG_CMD_ERR_CODE_LAST VNIC_PLCMODES_CFG_CMD_ERR_CODE_INVALID_HDS_THRESHOLD
7136+
u8 unused_0[7];
7137+
};
7138+
70857139
/* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
70867140
struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
70877141
__le16 req_type;
@@ -7131,15 +7185,16 @@ struct hwrm_ring_alloc_input {
71317185
__le16 target_id;
71327186
__le64 resp_addr;
71337187
__le32 enables;
7134-
#define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL
7135-
#define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL
7136-
#define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL
7137-
#define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL
7138-
#define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL
7139-
#define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL
7140-
#define RING_ALLOC_REQ_ENABLES_SCHQ_ID 0x200UL
7141-
#define RING_ALLOC_REQ_ENABLES_MPC_CHNLS_TYPE 0x400UL
7142-
#define RING_ALLOC_REQ_ENABLES_STEERING_TAG_VALID 0x800UL
7188+
#define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL
7189+
#define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL
7190+
#define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL
7191+
#define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL
7192+
#define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL
7193+
#define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL
7194+
#define RING_ALLOC_REQ_ENABLES_SCHQ_ID 0x200UL
7195+
#define RING_ALLOC_REQ_ENABLES_MPC_CHNLS_TYPE 0x400UL
7196+
#define RING_ALLOC_REQ_ENABLES_STEERING_TAG_VALID 0x800UL
7197+
#define RING_ALLOC_REQ_ENABLES_RX_RATE_PROFILE_VALID 0x1000UL
71437198
u8 ring_type;
71447199
#define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL
71457200
#define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL
@@ -7226,7 +7281,11 @@ struct hwrm_ring_alloc_input {
72267281
#define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RE_CFA 0x3UL
72277282
#define RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 0x4UL
72287283
#define RING_ALLOC_REQ_MPC_CHNLS_TYPE_LAST RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE
7229-
u8 unused_4[2];
7284+
u8 rx_rate_profile_sel;
7285+
#define RING_ALLOC_REQ_RX_RATE_PROFILE_SEL_DEFAULT 0x0UL
7286+
#define RING_ALLOC_REQ_RX_RATE_PROFILE_SEL_POLL_MODE 0x1UL
7287+
#define RING_ALLOC_REQ_RX_RATE_PROFILE_SEL_LAST RING_ALLOC_REQ_RX_RATE_PROFILE_SEL_POLL_MODE
7288+
u8 unused_4;
72307289
__le64 cq_handle;
72317290
};
72327291

@@ -9122,6 +9181,39 @@ struct pcie_ctx_hw_stats {
91229181
__le64 pcie_recovery_histogram;
91239182
};
91249183

9184+
/* pcie_ctx_hw_stats_v2 (size:4096b/512B) */
9185+
struct pcie_ctx_hw_stats_v2 {
9186+
__le64 pcie_pl_signal_integrity;
9187+
__le64 pcie_dl_signal_integrity;
9188+
__le64 pcie_tl_signal_integrity;
9189+
__le64 pcie_link_integrity;
9190+
__le64 pcie_tx_traffic_rate;
9191+
__le64 pcie_rx_traffic_rate;
9192+
__le64 pcie_tx_dllp_statistics;
9193+
__le64 pcie_rx_dllp_statistics;
9194+
__le64 pcie_equalization_time;
9195+
__le32 pcie_ltssm_histogram[4];
9196+
__le64 pcie_recovery_histogram;
9197+
__le32 pcie_tl_credit_nph_histogram[8];
9198+
__le32 pcie_tl_credit_ph_histogram[8];
9199+
__le32 pcie_tl_credit_pd_histogram[8];
9200+
__le32 pcie_cmpl_latest_times[4];
9201+
__le32 pcie_cmpl_longest_time;
9202+
__le32 pcie_cmpl_shortest_time;
9203+
__le32 unused_0[2];
9204+
__le32 pcie_cmpl_latest_headers[4][4];
9205+
__le32 pcie_cmpl_longest_headers[4][4];
9206+
__le32 pcie_cmpl_shortest_headers[4][4];
9207+
__le32 pcie_wr_latency_histogram[12];
9208+
__le32 pcie_wr_latency_all_normal_count;
9209+
__le32 unused_1;
9210+
__le64 pcie_posted_packet_count;
9211+
__le64 pcie_non_posted_packet_count;
9212+
__le64 pcie_other_packet_count;
9213+
__le64 pcie_blocked_packet_count;
9214+
__le64 pcie_cmpl_packet_count;
9215+
};
9216+
91259217
/* hwrm_stat_generic_qstats_input (size:256b/32B) */
91269218
struct hwrm_stat_generic_qstats_input {
91279219
__le16 req_type;
@@ -9317,6 +9409,9 @@ struct hwrm_struct_hdr {
93179409
#define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_UDCC_RTT_BUCKET_BOUND
93189410
__le16 len;
93199411
u8 version;
9412+
#define STRUCT_HDR_VERSION_0 0x0UL
9413+
#define STRUCT_HDR_VERSION_1 0x1UL
9414+
#define STRUCT_HDR_VERSION_LAST STRUCT_HDR_VERSION_1
93209415
u8 count;
93219416
__le16 subtype;
93229417
__le16 next_offset;

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