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Fan Gong
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hinic3: module initialization and tx/rx logic
This is [1/3] part of hinic3 Ethernet driver initial submission. With this patch hinic3 is a valid kernel module but non-functional driver. The driver parts contained in this patch: Module initialization. PCI driver registration but with empty id_table. Auxiliary driver registration. Net device_ops registration but open/stop are empty stubs. tx/rx logic. All major data structures of the driver are fully introduced with the code that uses them but without their initialization code that requires management interface with the hw. Co-developed-by: Xin Guo <guoxin09@huawei.com> Signed-off-by: Xin Guo <guoxin09@huawei.com> Signed-off-by: Fan Gong <gongfan1@huawei.com> Co-developed-by: Gur Stavi <gur.stavi@huawei.com> Signed-off-by: Gur Stavi <gur.stavi@huawei.com> Link: https://patch.msgid.link/76a137ffdfe115c737c2c224f0c93b60ba53cc16.1747736586.git.gur.stavi@huawei.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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‎Documentation/networking/device_drivers/ethernet/huawei/hinic3.rst‎

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.. SPDX-License-Identifier: GPL-2.0
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=====================================================================
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Linux kernel driver for Huawei Ethernet Device Driver (hinic3) family
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=====================================================================
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Overview
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========
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The hinic3 is a network interface card (NIC) for Data Center. It supports
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a range of link-speed devices (10GE, 25GE, 100GE, etc.). The hinic3
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devices can have multiple physical forms: LOM (Lan on Motherboard) NIC,
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PCIe standard NIC, OCP (Open Compute Project) NIC, etc.
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The hinic3 driver supports the following features:
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- IPv4/IPv6 TCP/UDP checksum offload
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- TSO (TCP Segmentation Offload), LRO (Large Receive Offload)
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- RSS (Receive Side Scaling)
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- MSI-X interrupt aggregation configuration and interrupt adaptation.
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- SR-IOV (Single Root I/O Virtualization).
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Content
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=======
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- Supported PCI vendor ID/device IDs
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- Source Code Structure of Hinic3 Driver
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- Management Interface
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Supported PCI vendor ID/device IDs
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==================================
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19e5:0222 - hinic3 PF/PPF
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19e5:375F - hinic3 VF
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Prime Physical Function (PPF) is responsible for the management of the
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whole NIC card. For example, clock synchronization between the NIC and
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the host. Any PF may serve as a PPF. The PPF is selected dynamically.
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Source Code Structure of Hinic3 Driver
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======================================
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======================== ================================================
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hinic3_pci_id_tbl.h Supported device IDs
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hinic3_hw_intf.h Interface between HW and driver
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hinic3_queue_common.[ch] Common structures and methods for NIC queues
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hinic3_common.[ch] Encapsulation of memory operations in Linux
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hinic3_csr.h Register definitions in the BAR
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hinic3_hwif.[ch] Interface for BAR
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hinic3_eqs.[ch] Interface for AEQs and CEQs
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hinic3_mbox.[ch] Interface for mailbox
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hinic3_mgmt.[ch] Management interface based on mailbox and AEQ
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hinic3_wq.[ch] Work queue data structures and interface
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hinic3_cmdq.[ch] Command queue is used to post command to HW
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hinic3_hwdev.[ch] HW structures and methods abstractions
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hinic3_lld.[ch] Auxiliary driver adaptation layer
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hinic3_hw_comm.[ch] Interface for common HW operations
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hinic3_mgmt_interface.h Interface between firmware and driver
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hinic3_hw_cfg.[ch] Interface for HW configuration
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hinic3_irq.c Interrupt request
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hinic3_netdev_ops.c Operations registered to Linux kernel stack
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hinic3_nic_dev.h NIC structures and methods abstractions
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hinic3_main.c Main Linux kernel driver
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hinic3_nic_cfg.[ch] NIC service configuration
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hinic3_nic_io.[ch] Management plane interface for TX and RX
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hinic3_rss.[ch] Interface for Receive Side Scaling (RSS)
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hinic3_rx.[ch] Interface for transmit
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hinic3_tx.[ch] Interface for receive
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hinic3_ethtool.c Interface for ethtool operations (ops)
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hinic3_filter.c Interface for MAC address
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======================== ================================================
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Management Interface
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====================
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Asynchronous Event Queue (AEQ)
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------------------------------
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AEQ receives high priority events from the HW over a descriptor queue.
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Every descriptor is a fixed size of 64 bytes. AEQ can receive solicited or
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unsolicited events. Every device, VF or PF, can have up to 4 AEQs.
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Every AEQ is associated to a dedicated IRQ. AEQ can receive multiple types
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of events, but in practice the hinic3 driver ignores all events except for
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2 mailbox related events.
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Mailbox
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-------
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Mailbox is a communication mechanism between the hinic3 driver and the HW.
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Each device has an independent mailbox. Driver can use the mailbox to send
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requests to management. Driver receives mailbox messages, such as responses
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to requests, over the AEQ (using event HINIC3_AEQ_FOR_MBOX). Due to the
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limited size of mailbox data register, mailbox messages are sent
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segment-by-segment.
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Every device can use its mailbox to post request to firmware. The mailbox
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can also be used to post requests and responses between the PF and its VFs.
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Completion Event Queue (CEQ)
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----------------------------
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The implementation of CEQ is the same as AEQ. It receives completion events
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from HW over a fixed size descriptor of 32 bits. Every device can have up
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to 32 CEQs. Every CEQ has a dedicated IRQ. CEQ only receives solicited
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events that are responses to requests from the driver. CEQ can receive
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multiple types of events, but in practice the hinic3 driver ignores all
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events except for HINIC3_CMDQ that represents completion of previously
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posted commands on a cmdq.
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Command Queue (cmdq)
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--------------------
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Every cmdq has a dedicated work queue on which commands are posted.
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Commands on the work queue are fixed size descriptor of size 64 bytes.
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Completion of a command will be indicated using ctrl bits in the
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descriptor that carried the command. Notification of command completions
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will also be provided via event on CEQ. Every device has 4 command queues
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that are initialized as a set (called cmdqs), each with its own type.
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Hinic3 driver only uses type HINIC3_CMDQ_SYNC.
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Work Queues(WQ)
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---------------
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Work queues are logical arrays of fixed size WQEs. The array may be spread
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over multiple non-contiguous pages using indirection table. Work queues are
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used by I/O queues and command queues.
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Global function ID
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------------------
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Every function, PF or VF, has a unique ordinal identification within the device.
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Many management commands (mbox or cmdq) contain this ID so HW can apply the
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command effect to the right function.
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PF is allowed to post management commands to a subordinate VF by specifying the
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VFs ID. A VF must provide its own ID. Anti-spoofing in the HW will cause
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command from a VF to fail if it contains the wrong ID.
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‎Documentation/networking/device_drivers/ethernet/index.rst‎

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freescale/gianfar
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google/gve
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huawei/hinic
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huawei/hinic3
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intel/e100
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intel/e1000
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intel/e1000e

‎MAINTAINERS‎

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F: Documentation/networking/device_drivers/ethernet/huawei/hinic.rst
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F: drivers/net/ethernet/huawei/hinic/
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HUAWEI 3RD GEN ETHERNET DRIVER
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M: Fan Gong <gongfan1@huawei.com>
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L: netdev@vger.kernel.org
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S: Maintained
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F: Documentation/networking/device_drivers/ethernet/huawei/hinic3.rst
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F: drivers/net/ethernet/huawei/hinic3/
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1096610973
HUAWEI MATEBOOK E GO EMBEDDED CONTROLLER DRIVER
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M: Pengyu Luo <mitltlatltl@gmail.com>
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S: Maintained

‎drivers/net/ethernet/huawei/Kconfig‎

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if NET_VENDOR_HUAWEI
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source "drivers/net/ethernet/huawei/hinic/Kconfig"
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source "drivers/net/ethernet/huawei/hinic3/Kconfig"
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endif # NET_VENDOR_HUAWEI

‎drivers/net/ethernet/huawei/Makefile‎

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#
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obj-$(CONFIG_HINIC) += hinic/
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obj-$(CONFIG_HINIC3) += hinic3/

‎drivers/net/ethernet/huawei/hinic3/Kconfig‎

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# SPDX-License-Identifier: GPL-2.0-only
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#
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# Huawei driver configuration
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#
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config HINIC3
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tristate "Huawei 3rd generation network adapters (HINIC3) support"
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# Fields of HW and management structures are little endian and are
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# currently not converted
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depends on !CPU_BIG_ENDIAN
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depends on X86 || ARM64 || COMPILE_TEST
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depends on PCI_MSI && 64BIT
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select AUXILIARY_BUS
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select PAGE_POOL
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help
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This driver supports HiNIC 3rd gen Network Adapter (HINIC3).
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The driver is supported on X86_64 and ARM64 little endian.
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To compile this driver as a module, choose M here.
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The module will be called hinic3.

‎drivers/net/ethernet/huawei/hinic3/Makefile‎

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# SPDX-License-Identifier: GPL-2.0
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# Copyright (c) Huawei Technologies Co., Ltd. 2025. All rights reserved.
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obj-$(CONFIG_HINIC3) += hinic3.o
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hinic3-objs := hinic3_common.o \
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hinic3_hw_cfg.o \
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hinic3_hw_comm.o \
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hinic3_hwdev.o \
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hinic3_hwif.o \
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hinic3_irq.o \
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hinic3_lld.o \
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hinic3_main.o \
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hinic3_mbox.o \
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hinic3_netdev_ops.o \
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hinic3_nic_cfg.o \
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hinic3_nic_io.o \
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hinic3_queue_common.o \
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hinic3_rx.o \
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hinic3_tx.o \
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hinic3_wq.o

‎drivers/net/ethernet/huawei/hinic3/hinic3_common.c‎

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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) Huawei Technologies Co., Ltd. 2025. All rights reserved.
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include "hinic3_common.h"
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int hinic3_dma_zalloc_coherent_align(struct device *dev, u32 size, u32 align,
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gfp_t flag,
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struct hinic3_dma_addr_align *mem_align)
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{
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dma_addr_t paddr, align_paddr;
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void *vaddr, *align_vaddr;
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u32 real_size = size;
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vaddr = dma_alloc_coherent(dev, real_size, &paddr, flag);
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if (!vaddr)
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return -ENOMEM;
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align_paddr = ALIGN(paddr, align);
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if (align_paddr == paddr) {
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align_vaddr = vaddr;
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goto out;
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}
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dma_free_coherent(dev, real_size, vaddr, paddr);
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/* realloc memory for align */
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real_size = size + align;
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vaddr = dma_alloc_coherent(dev, real_size, &paddr, flag);
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if (!vaddr)
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return -ENOMEM;
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align_paddr = ALIGN(paddr, align);
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align_vaddr = vaddr + (align_paddr - paddr);
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out:
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mem_align->real_size = real_size;
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mem_align->ori_vaddr = vaddr;
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mem_align->ori_paddr = paddr;
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mem_align->align_vaddr = align_vaddr;
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mem_align->align_paddr = align_paddr;
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return 0;
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}
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void hinic3_dma_free_coherent_align(struct device *dev,
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struct hinic3_dma_addr_align *mem_align)
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{
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dma_free_coherent(dev, mem_align->real_size,
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mem_align->ori_vaddr, mem_align->ori_paddr);
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}

‎drivers/net/ethernet/huawei/hinic3/hinic3_common.h‎

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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) Huawei Technologies Co., Ltd. 2025. All rights reserved. */
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#ifndef _HINIC3_COMMON_H_
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#define _HINIC3_COMMON_H_
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#include <linux/device.h>
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#define HINIC3_MIN_PAGE_SIZE 0x1000
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struct hinic3_dma_addr_align {
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u32 real_size;
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void *ori_vaddr;
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dma_addr_t ori_paddr;
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void *align_vaddr;
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dma_addr_t align_paddr;
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};
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int hinic3_dma_zalloc_coherent_align(struct device *dev, u32 size, u32 align,
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gfp_t flag,
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struct hinic3_dma_addr_align *mem_align);
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void hinic3_dma_free_coherent_align(struct device *dev,
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struct hinic3_dma_addr_align *mem_align);
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#endif

‎drivers/net/ethernet/huawei/hinic3/hinic3_hw_cfg.c‎

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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) Huawei Technologies Co., Ltd. 2025. All rights reserved.
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#include <linux/device.h>
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#include "hinic3_hw_cfg.h"
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#include "hinic3_hwdev.h"
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#include "hinic3_hwif.h"
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#include "hinic3_mbox.h"
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bool hinic3_support_nic(struct hinic3_hwdev *hwdev)
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{
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return hwdev->cfg_mgmt->cap.supp_svcs_bitmap &
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BIT(HINIC3_SERVICE_T_NIC);
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}
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u16 hinic3_func_max_qnum(struct hinic3_hwdev *hwdev)
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{
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return hwdev->cfg_mgmt->cap.nic_svc_cap.max_sqs;
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}
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u8 hinic3_physical_port_id(struct hinic3_hwdev *hwdev)
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{
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return hwdev->cfg_mgmt->cap.port_id;
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}

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