@@ -60,7 +60,8 @@ static inline void clear_page_cpu(void *page)
6060 " .set noreorder \n"
6161#ifdef CONFIG_CPU_HAS_PREFETCH
6262 " daddiu %0, %0, 128 \n"
63- " pref " SB1_PREF_STORE_STREAMED_HINT ", -128(%0) \n" /* Prefetch the first 4 lines */
63+ " pref " SB1_PREF_STORE_STREAMED_HINT ", -128(%0) \n"
64+ /* Prefetch the first 4 lines */
6465 " pref " SB1_PREF_STORE_STREAMED_HINT ", -96(%0) \n"
6566 " pref " SB1_PREF_STORE_STREAMED_HINT ", -64(%0) \n"
6667 " pref " SB1_PREF_STORE_STREAMED_HINT ", -32(%0) \n"
@@ -106,7 +107,8 @@ static inline void copy_page_cpu(void *to, void *from)
106107#ifdef CONFIG_CPU_HAS_PREFETCH
107108 " daddiu %0, %0, 128 \n"
108109 " daddiu %1, %1, 128 \n"
109- " pref " SB1_PREF_LOAD_STREAMED_HINT ", -128(%0)\n" /* Prefetch the first 4 lines */
110+ " pref " SB1_PREF_LOAD_STREAMED_HINT ", -128(%0)\n"
111+ /* Prefetch the first 4 lines */
110112 " pref " SB1_PREF_STORE_STREAMED_HINT ", -128(%1)\n"
111113 " pref " SB1_PREF_LOAD_STREAMED_HINT ", -96(%0)\n"
112114 " pref " SB1_PREF_STORE_STREAMED_HINT ", -96(%1)\n"
@@ -207,15 +209,18 @@ typedef struct dmadscr_s {
207209 u64 pad_b ;
208210} dmadscr_t ;
209211
210- static dmadscr_t page_descr [DM_NUM_CHANNELS ] __attribute__((aligned (SMP_CACHE_BYTES )));
212+ static dmadscr_t page_descr [DM_NUM_CHANNELS ]
213+ __attribute__((aligned (SMP_CACHE_BYTES )));
211214
212215void sb1_dma_init (void )
213216{
214217 int i ;
215218
216219 for (i = 0 ; i < DM_NUM_CHANNELS ; i ++ ) {
217- u64 base_val = (u64 )CPHYSADDR (& page_descr [i ]) | V_DM_DSCR_BASE_RINGSZ (1 );
218- void * base_reg = (void * )IOADDR (A_DM_REGISTER (i , R_DM_DSCR_BASE ));
220+ const u64 base_val = CPHYSADDR (& page_descr [i ]) |
221+ V_DM_DSCR_BASE_RINGSZ (1 );
222+ volatile void * base_reg =
223+ IOADDR (A_DM_REGISTER (i , R_DM_DSCR_BASE ));
219224
220225 __raw_writeq (base_val , base_reg );
221226 __raw_writeq (base_val | M_DM_DSCR_BASE_RESET , base_reg );
@@ -225,14 +230,15 @@ void sb1_dma_init(void)
225230
226231void clear_page (void * page )
227232{
228- u64 to_phys = ( u64 ) CPHYSADDR (page );
233+ u64 to_phys = CPHYSADDR (page );
229234 unsigned int cpu = smp_processor_id ();
230235
231236 /* if the page is not in KSEG0, use old way */
232237 if ((long )KSEGX (page ) != (long )CKSEG0 )
233238 return clear_page_cpu (page );
234239
235- page_descr [cpu ].dscr_a = to_phys | M_DM_DSCRA_ZERO_MEM | M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT ;
240+ page_descr [cpu ].dscr_a = to_phys | M_DM_DSCRA_ZERO_MEM |
241+ M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT ;
236242 page_descr [cpu ].dscr_b = V_DM_DSCRB_SRC_LENGTH (PAGE_SIZE );
237243 __raw_writeq (1 , IOADDR (A_DM_REGISTER (cpu , R_DM_DSCR_COUNT )));
238244
@@ -248,24 +254,25 @@ void clear_page(void *page)
248254
249255void copy_page (void * to , void * from )
250256{
251- u64 from_phys = ( u64 ) CPHYSADDR (from );
252- u64 to_phys = ( u64 ) CPHYSADDR (to );
257+ u64 from_phys = CPHYSADDR (from );
258+ u64 to_phys = CPHYSADDR (to );
253259 unsigned int cpu = smp_processor_id ();
254260
255261 /* if any page is not in KSEG0, use old way */
256262 if ((long )KSEGX (to ) != (long )CKSEG0
257263 || (long )KSEGX (from ) != (long )CKSEG0 )
258264 return copy_page_cpu (to , from );
259265
260- page_descr [cpu ].dscr_a = to_phys | M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT ;
266+ page_descr [cpu ].dscr_a = to_phys | M_DM_DSCRA_L2C_DEST |
267+ M_DM_DSCRA_INTERRUPT ;
261268 page_descr [cpu ].dscr_b = from_phys | V_DM_DSCRB_SRC_LENGTH (PAGE_SIZE );
262- __raw_writeq (1 , ( void * ) IOADDR (A_DM_REGISTER (cpu , R_DM_DSCR_COUNT )));
269+ __raw_writeq (1 , IOADDR (A_DM_REGISTER (cpu , R_DM_DSCR_COUNT )));
263270
264271 /*
265272 * Don't really want to do it this way, but there's no
266273 * reliable way to delay completion detection.
267274 */
268- while (!(__raw_readq (( void * ) IOADDR (A_DM_REGISTER (cpu , R_DM_DSCR_BASE_DEBUG )))
275+ while (!(__raw_readq (IOADDR (A_DM_REGISTER (cpu , R_DM_DSCR_BASE_DEBUG )))
269276 & M_DM_DSCR_BASE_INTERRUPT ))
270277 ;
271278 __raw_readq (IOADDR (A_DM_REGISTER (cpu , R_DM_DSCR_BASE )));
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