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charleskeepaxbroonie
charleskeepax
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broonie
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ASoC: rt722-sdca: Make use of new expanded MBQ regmap
Now the MBQ regmap implementation handles multiple sizes, this driver can combine its two register maps into one. So remove mbq_regmap and combine all the registers into regmap. Also as rt722_sdca_adc_mux_get/put() only exist to access mbq_regmap, rather than doing any processing, these can now be dropped and the normal DAPM helpers used. Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.dev> Link: https://patch.msgid.link/20250107154408.814455-7-ckeepax@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
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+105
-214
lines changed

4 files changed

+105
-214
lines changed

‎sound/soc/codecs/rt722-sdca-sdw.c‎

Lines changed: 26 additions & 55 deletions
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616
#include "rt722-sdca.h"
1717
#include "rt722-sdca-sdw.h"
1818

19-
static bool rt722_sdca_readable_register(struct device *dev, unsigned int reg)
19+
static int rt722_sdca_mbq_size(struct device *dev, unsigned int reg)
2020
{
2121
switch (reg) {
2222
case 0x2f01 ... 0x2f0a:
@@ -73,32 +73,7 @@ static bool rt722_sdca_readable_register(struct device *dev, unsigned int reg)
7373
case SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_CS31,
7474
RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
7575
case RT722_BUF_ADDR_HID1 ... RT722_BUF_ADDR_HID2:
76-
return true;
77-
default:
78-
return false;
79-
}
80-
}
81-
82-
static bool rt722_sdca_volatile_register(struct device *dev, unsigned int reg)
83-
{
84-
switch (reg) {
85-
case 0x2f01:
86-
case 0x2f54:
87-
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49, RT722_SDCA_CTL_DETECTED_MODE,
88-
0):
89-
case SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, RT722_SDCA_CTL_HIDTX_CURRENT_OWNER,
90-
0) ... SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01,
91-
RT722_SDCA_CTL_HIDTX_MESSAGE_LENGTH, 0):
92-
case RT722_BUF_ADDR_HID1 ... RT722_BUF_ADDR_HID2:
93-
return true;
94-
default:
95-
return false;
96-
}
97-
}
98-
99-
static bool rt722_sdca_mbq_readable_register(struct device *dev, unsigned int reg)
100-
{
101-
switch (reg) {
76+
return 1;
10277
case 0x2000000 ... 0x2000024:
10378
case 0x2000029 ... 0x200004a:
10479
case 0x2000051 ... 0x2000052:
@@ -151,15 +126,32 @@ static bool rt722_sdca_mbq_readable_register(struct device *dev, unsigned int re
151126
RT722_SDCA_CTL_FU_CH_GAIN, CH_L):
152127
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44,
153128
RT722_SDCA_CTL_FU_CH_GAIN, CH_R):
154-
return true;
129+
return 2;
155130
default:
156-
return false;
131+
return 0;
157132
}
158133
}
159134

160-
static bool rt722_sdca_mbq_volatile_register(struct device *dev, unsigned int reg)
135+
static struct regmap_sdw_mbq_cfg rt722_mbq_config = {
136+
.mbq_size = rt722_sdca_mbq_size,
137+
};
138+
139+
static bool rt722_sdca_readable_register(struct device *dev, unsigned int reg)
140+
{
141+
return rt722_sdca_mbq_size(dev, reg) > 0;
142+
}
143+
144+
static bool rt722_sdca_volatile_register(struct device *dev, unsigned int reg)
161145
{
162146
switch (reg) {
147+
case 0x2f01:
148+
case 0x2f54:
149+
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49, RT722_SDCA_CTL_DETECTED_MODE,
150+
0):
151+
case SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, RT722_SDCA_CTL_HIDTX_CURRENT_OWNER,
152+
0) ... SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01,
153+
RT722_SDCA_CTL_HIDTX_MESSAGE_LENGTH, 0):
154+
case RT722_BUF_ADDR_HID1 ... RT722_BUF_ADDR_HID2:
163155
case 0x2000000:
164156
case 0x200000d:
165157
case 0x2000019:
@@ -178,7 +170,7 @@ static bool rt722_sdca_mbq_volatile_register(struct device *dev, unsigned int re
178170

179171
static const struct regmap_config rt722_sdca_regmap = {
180172
.reg_bits = 32,
181-
.val_bits = 8,
173+
.val_bits = 16,
182174
.readable_reg = rt722_sdca_readable_register,
183175
.volatile_reg = rt722_sdca_volatile_register,
184176
.max_register = 0x44ffffff,
@@ -189,20 +181,6 @@ static const struct regmap_config rt722_sdca_regmap = {
189181
.use_single_write = true,
190182
};
191183

192-
static const struct regmap_config rt722_sdca_mbq_regmap = {
193-
.name = "sdw-mbq",
194-
.reg_bits = 32,
195-
.val_bits = 16,
196-
.readable_reg = rt722_sdca_mbq_readable_register,
197-
.volatile_reg = rt722_sdca_mbq_volatile_register,
198-
.max_register = 0x41000312,
199-
.reg_defaults = rt722_sdca_mbq_defaults,
200-
.num_reg_defaults = ARRAY_SIZE(rt722_sdca_mbq_defaults),
201-
.cache_type = REGCACHE_MAPLE,
202-
.use_single_read = true,
203-
.use_single_write = true,
204-
};
205-
206184
static int rt722_sdca_update_status(struct sdw_slave *slave,
207185
enum sdw_slave_status status)
208186
{
@@ -412,18 +390,14 @@ static const struct sdw_slave_ops rt722_sdca_slave_ops = {
412390
static int rt722_sdca_sdw_probe(struct sdw_slave *slave,
413391
const struct sdw_device_id *id)
414392
{
415-
struct regmap *regmap, *mbq_regmap;
393+
struct regmap *regmap;
416394

417395
/* Regmap Initialization */
418-
mbq_regmap = devm_regmap_init_sdw_mbq(slave, &rt722_sdca_mbq_regmap);
419-
if (IS_ERR(mbq_regmap))
420-
return PTR_ERR(mbq_regmap);
421-
422-
regmap = devm_regmap_init_sdw(slave, &rt722_sdca_regmap);
396+
regmap = devm_regmap_init_sdw_mbq_cfg(slave, &rt722_sdca_regmap, &rt722_mbq_config);
423397
if (IS_ERR(regmap))
424398
return PTR_ERR(regmap);
425399

426-
return rt722_sdca_init(&slave->dev, regmap, mbq_regmap, slave);
400+
return rt722_sdca_init(&slave->dev, regmap, slave);
427401
}
428402

429403
static int rt722_sdca_sdw_remove(struct sdw_slave *slave)
@@ -461,7 +435,6 @@ static int __maybe_unused rt722_sdca_dev_suspend(struct device *dev)
461435
cancel_delayed_work_sync(&rt722->jack_btn_check_work);
462436

463437
regcache_cache_only(rt722->regmap, true);
464-
regcache_cache_only(rt722->mbq_regmap, true);
465438

466439
return 0;
467440
}
@@ -531,8 +504,6 @@ static int __maybe_unused rt722_sdca_dev_resume(struct device *dev)
531504
slave->unattach_request = 0;
532505
regcache_cache_only(rt722->regmap, false);
533506
regcache_sync(rt722->regmap);
534-
regcache_cache_only(rt722->mbq_regmap, false);
535-
regcache_sync(rt722->mbq_regmap);
536507
return 0;
537508
}
538509

‎sound/soc/codecs/rt722-sdca-sdw.h‎

Lines changed: 48 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -31,50 +31,9 @@ static const struct reg_default rt722_sdca_reg_defaults[] = {
3131
{ 0x2f5b, 0x07 },
3232
{ 0x2f5c, 0x27 },
3333
{ 0x2f5d, 0x07 },
34-
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS01, RT722_SDCA_CTL_SAMPLE_FREQ_INDEX,
35-
0), 0x09 },
36-
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS11, RT722_SDCA_CTL_SAMPLE_FREQ_INDEX,
37-
0), 0x09 },
38-
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, RT722_SDCA_CTL_REQ_POWER_STATE,
39-
0), 0x03 },
40-
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, RT722_SDCA_CTL_REQ_POWER_STATE,
41-
0), 0x03 },
42-
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, RT722_SDCA_CTL_FU_MUTE, CH_L),
43-
0x01 },
44-
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, RT722_SDCA_CTL_FU_MUTE, CH_R),
45-
0x01 },
46-
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, RT722_SDCA_CTL_FU_MUTE, CH_L),
47-
0x01 },
48-
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, RT722_SDCA_CTL_FU_MUTE, CH_R),
49-
0x01 },
50-
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_CS1F, RT722_SDCA_CTL_SAMPLE_FREQ_INDEX,
51-
0), 0x09 },
52-
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_MUTE, CH_01),
53-
0x01 },
54-
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_MUTE, CH_02),
55-
0x01 },
56-
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_MUTE, CH_03),
57-
0x01 },
58-
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_MUTE, CH_04),
59-
0x01 },
60-
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, RT722_SDCA_CTL_REQ_POWER_STATE, 0),
61-
0x03 },
62-
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_IT26, RT722_SDCA_CTL_VENDOR_DEF, 0),
63-
0x00 },
64-
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_CS31, RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
65-
0x09 },
66-
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, RT722_SDCA_CTL_FU_MUTE, CH_L),
67-
0x01 },
68-
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, RT722_SDCA_CTL_FU_MUTE, CH_R),
69-
0x01 },
70-
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, RT722_SDCA_CTL_REQ_POWER_STATE, 0),
71-
0x03 },
72-
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_OT23, RT722_SDCA_CTL_VENDOR_DEF, 0), 0x00 },
73-
};
74-
75-
static const struct reg_default rt722_sdca_mbq_defaults[] = {
7634
{ 0x200003c, 0xc214 },
7735
{ 0x2000046, 0x8004 },
36+
{ 0x5810000, 0x702d },
7837
{ 0x6100006, 0x0005 },
7938
{ 0x6100010, 0x2630 },
8039
{ 0x6100011, 0x152f },
@@ -86,27 +45,34 @@ static const struct reg_default rt722_sdca_mbq_defaults[] = {
8645
{ 0x6100028, 0x2a2a },
8746
{ 0x6100029, 0x4141 },
8847
{ 0x6100055, 0x0000 },
89-
{ 0x5810000, 0x702d },
48+
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, RT722_SDCA_CTL_FU_MUTE, CH_L),
49+
0x01 },
50+
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, RT722_SDCA_CTL_FU_MUTE, CH_R),
51+
0x01 },
9052
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, RT722_SDCA_CTL_FU_VOLUME,
9153
CH_L), 0x0000 },
9254
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, RT722_SDCA_CTL_FU_VOLUME,
9355
CH_R), 0x0000 },
56+
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, RT722_SDCA_CTL_FU_MUTE, CH_L),
57+
0x01 },
58+
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, RT722_SDCA_CTL_FU_MUTE, CH_R),
59+
0x01 },
9460
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, RT722_SDCA_CTL_FU_VOLUME,
9561
CH_L), 0x0000 },
9662
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, RT722_SDCA_CTL_FU_VOLUME,
9763
CH_R), 0x0000 },
64+
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, RT722_SDCA_CTL_REQ_POWER_STATE,
65+
0), 0x03 },
66+
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS01, RT722_SDCA_CTL_SAMPLE_FREQ_INDEX,
67+
0), 0x09 },
68+
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS11, RT722_SDCA_CTL_SAMPLE_FREQ_INDEX,
69+
0), 0x09 },
70+
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, RT722_SDCA_CTL_REQ_POWER_STATE,
71+
0), 0x03 },
9872
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44, RT722_SDCA_CTL_FU_CH_GAIN,
9973
CH_L), 0x0000 },
10074
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44, RT722_SDCA_CTL_FU_CH_GAIN,
10175
CH_R), 0x0000 },
102-
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME,
103-
CH_01), 0x0000 },
104-
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME,
105-
CH_02), 0x0000 },
106-
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME,
107-
CH_03), 0x0000 },
108-
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME,
109-
CH_04), 0x0000 },
11076
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_FU15, RT722_SDCA_CTL_FU_CH_GAIN, CH_01),
11177
0x0000 },
11278
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_FU15, RT722_SDCA_CTL_FU_CH_GAIN, CH_02),
@@ -115,10 +81,41 @@ static const struct reg_default rt722_sdca_mbq_defaults[] = {
11581
0x0000 },
11682
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_FU15, RT722_SDCA_CTL_FU_CH_GAIN, CH_04),
11783
0x0000 },
84+
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_MUTE, CH_01),
85+
0x01 },
86+
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_MUTE, CH_02),
87+
0x01 },
88+
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_MUTE, CH_03),
89+
0x01 },
90+
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_MUTE, CH_04),
91+
0x01 },
92+
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME,
93+
CH_01), 0x0000 },
94+
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME,
95+
CH_02), 0x0000 },
96+
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME,
97+
CH_03), 0x0000 },
98+
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME,
99+
CH_04), 0x0000 },
100+
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, RT722_SDCA_CTL_REQ_POWER_STATE, 0),
101+
0x03 },
102+
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_CS1F, RT722_SDCA_CTL_SAMPLE_FREQ_INDEX,
103+
0), 0x09 },
104+
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_IT26, RT722_SDCA_CTL_VENDOR_DEF, 0),
105+
0x00 },
106+
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, RT722_SDCA_CTL_FU_MUTE, CH_L),
107+
0x01 },
108+
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, RT722_SDCA_CTL_FU_MUTE, CH_R),
109+
0x01 },
118110
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, RT722_SDCA_CTL_FU_VOLUME, CH_L),
119111
0x0000 },
120112
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, RT722_SDCA_CTL_FU_VOLUME, CH_R),
121113
0x0000 },
114+
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, RT722_SDCA_CTL_REQ_POWER_STATE, 0),
115+
0x03 },
116+
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_CS31, RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
117+
0x09 },
118+
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_OT23, RT722_SDCA_CTL_VENDOR_DEF, 0), 0x00 },
122119
};
123120

124121
#endif /* __RT722_SDW_H__ */

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