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dt-bindings: PCI: Correct indentation and style in DTS example
DTS example in the bindings should be indented with 2- or 4-spaces and aligned with opening '- |', so correct any differences like 3-spaces or mixtures 2- and 4-spaces in one binding. No functional changes here, but saves some comments during reviews of new patches built on existing code. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20250324125202.81986-1-krzysztof.kozlowski@linaro.org
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‎Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml‎

Lines changed: 43 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -186,49 +186,48 @@ examples:
186186
#include <dt-bindings/interrupt-controller/arm-gic.h>
187187
188188
scb {
189-
#address-cells = <2>;
190-
#size-cells = <1>;
191-
pcie0: pcie@7d500000 {
192-
compatible = "brcm,bcm2711-pcie";
193-
reg = <0x0 0x7d500000 0x9310>;
194-
device_type = "pci";
195-
#address-cells = <3>;
196-
#size-cells = <2>;
197-
#interrupt-cells = <1>;
198-
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
199-
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
200-
interrupt-names = "pcie", "msi";
201-
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
202-
interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH
203-
0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH
204-
0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH
205-
0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
206-
207-
msi-parent = <&pcie0>;
208-
msi-controller;
209-
ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>;
210-
dma-ranges = <0x42000000 0x1 0x00000000 0x0 0x40000000 0x0 0x80000000>,
211-
<0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>;
212-
brcm,enable-ssc;
213-
brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>;
214-
215-
/* PCIe bridge, Root Port */
216-
pci@0,0 {
217-
#address-cells = <3>;
218-
#size-cells = <2>;
219-
reg = <0x0 0x0 0x0 0x0 0x0>;
220-
compatible = "pciclass,0604";
221-
device_type = "pci";
222-
vpcie3v3-supply = <&vreg7>;
223-
ranges;
224-
225-
/* PCIe endpoint */
226-
pci-ep@0,0 {
227-
assigned-addresses =
228-
<0x82010000 0x0 0xf8000000 0x6 0x00000000 0x0 0x2000>;
229-
reg = <0x0 0x0 0x0 0x0 0x0>;
230-
compatible = "pci14e4,1688";
231-
};
232-
};
189+
#address-cells = <2>;
190+
#size-cells = <1>;
191+
pcie0: pcie@7d500000 {
192+
compatible = "brcm,bcm2711-pcie";
193+
reg = <0x0 0x7d500000 0x9310>;
194+
device_type = "pci";
195+
#address-cells = <3>;
196+
#size-cells = <2>;
197+
#interrupt-cells = <1>;
198+
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
199+
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
200+
interrupt-names = "pcie", "msi";
201+
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
202+
interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH
203+
0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH
204+
0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH
205+
0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
206+
207+
msi-parent = <&pcie0>;
208+
msi-controller;
209+
ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>;
210+
dma-ranges = <0x42000000 0x1 0x00000000 0x0 0x40000000 0x0 0x80000000>,
211+
<0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>;
212+
brcm,enable-ssc;
213+
brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>;
214+
215+
/* PCIe bridge, Root Port */
216+
pci@0,0 {
217+
#address-cells = <3>;
218+
#size-cells = <2>;
219+
reg = <0x0 0x0 0x0 0x0 0x0>;
220+
compatible = "pciclass,0604";
221+
device_type = "pci";
222+
vpcie3v3-supply = <&vreg7>;
223+
ranges;
224+
225+
/* PCIe endpoint */
226+
pci-ep@0,0 {
227+
assigned-addresses = <0x82010000 0x0 0xf8000000 0x6 0x00000000 0x0 0x2000>;
228+
reg = <0x0 0x0 0x0 0x0 0x0>;
229+
compatible = "pci14e4,1688";
230+
};
233231
};
232+
};
234233
};

‎Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -37,14 +37,14 @@ examples:
3737
#size-cells = <2>;
3838
3939
pcie-ep@fc000000 {
40-
compatible = "cdns,cdns-pcie-ep";
41-
reg = <0x0 0xfc000000 0x0 0x01000000>,
42-
<0x0 0x80000000 0x0 0x40000000>;
43-
reg-names = "reg", "mem";
44-
cdns,max-outbound-regions = <16>;
45-
max-functions = /bits/ 8 <8>;
46-
phys = <&pcie_phy0>;
47-
phy-names = "pcie-phy";
40+
compatible = "cdns,cdns-pcie-ep";
41+
reg = <0x0 0xfc000000 0x0 0x01000000>,
42+
<0x0 0x80000000 0x0 0x40000000>;
43+
reg-names = "reg", "mem";
44+
cdns,max-outbound-regions = <16>;
45+
max-functions = /bits/ 8 <8>;
46+
phys = <&pcie_phy0>;
47+
phy-names = "pcie-phy";
4848
};
4949
};
5050
...

‎Documentation/devicetree/bindings/pci/intel,keembay-pcie-ep.yaml‎

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -53,17 +53,17 @@ examples:
5353
#include <dt-bindings/interrupt-controller/arm-gic.h>
5454
#include <dt-bindings/interrupt-controller/irq.h>
5555
pcie-ep@37000000 {
56-
compatible = "intel,keembay-pcie-ep";
57-
reg = <0x37000000 0x00001000>,
58-
<0x37100000 0x00001000>,
59-
<0x37300000 0x00001000>,
60-
<0x36000000 0x01000000>,
61-
<0x37800000 0x00000200>;
62-
reg-names = "dbi", "dbi2", "atu", "addr_space", "apb";
63-
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
64-
<GIC_SPI 108 IRQ_TYPE_EDGE_RISING>,
65-
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
66-
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
67-
interrupt-names = "pcie", "pcie_ev", "pcie_err", "pcie_mem_access";
68-
num-lanes = <2>;
56+
compatible = "intel,keembay-pcie-ep";
57+
reg = <0x37000000 0x00001000>,
58+
<0x37100000 0x00001000>,
59+
<0x37300000 0x00001000>,
60+
<0x36000000 0x01000000>,
61+
<0x37800000 0x00000200>;
62+
reg-names = "dbi", "dbi2", "atu", "addr_space", "apb";
63+
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
64+
<GIC_SPI 108 IRQ_TYPE_EDGE_RISING>,
65+
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
66+
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
67+
interrupt-names = "pcie", "pcie_ev", "pcie_err", "pcie_mem_access";
68+
num-lanes = <2>;
6969
};

‎Documentation/devicetree/bindings/pci/intel,keembay-pcie.yaml‎

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -75,23 +75,23 @@ examples:
7575
#define KEEM_BAY_A53_PCIE
7676
#define KEEM_BAY_A53_AUX_PCIE
7777
pcie@37000000 {
78-
compatible = "intel,keembay-pcie";
79-
reg = <0x37000000 0x00001000>,
80-
<0x37300000 0x00001000>,
81-
<0x36e00000 0x00200000>,
82-
<0x37800000 0x00000200>;
83-
reg-names = "dbi", "atu", "config", "apb";
84-
#address-cells = <3>;
85-
#size-cells = <2>;
86-
device_type = "pci";
87-
ranges = <0x02000000 0 0x36000000 0x36000000 0 0x00e00000>;
88-
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
89-
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
90-
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
91-
interrupt-names = "pcie", "pcie_ev", "pcie_err";
92-
clocks = <&scmi_clk KEEM_BAY_A53_PCIE>,
93-
<&scmi_clk KEEM_BAY_A53_AUX_PCIE>;
94-
clock-names = "master", "aux";
95-
reset-gpios = <&pca2 9 GPIO_ACTIVE_LOW>;
96-
num-lanes = <2>;
78+
compatible = "intel,keembay-pcie";
79+
reg = <0x37000000 0x00001000>,
80+
<0x37300000 0x00001000>,
81+
<0x36e00000 0x00200000>,
82+
<0x37800000 0x00000200>;
83+
reg-names = "dbi", "atu", "config", "apb";
84+
#address-cells = <3>;
85+
#size-cells = <2>;
86+
device_type = "pci";
87+
ranges = <0x02000000 0 0x36000000 0x36000000 0 0x00e00000>;
88+
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
89+
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
90+
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
91+
interrupt-names = "pcie", "pcie_ev", "pcie_err";
92+
clocks = <&scmi_clk KEEM_BAY_A53_PCIE>,
93+
<&scmi_clk KEEM_BAY_A53_AUX_PCIE>;
94+
clock-names = "master", "aux";
95+
reset-gpios = <&pca2 9 GPIO_ACTIVE_LOW>;
96+
num-lanes = <2>;
9797
};

‎Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml‎

Lines changed: 27 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -65,33 +65,33 @@ unevaluatedProperties: false
6565
examples:
6666
- |
6767
soc {
68-
#address-cells = <2>;
68+
#address-cells = <2>;
69+
#size-cells = <2>;
70+
pcie0: pcie@2030000000 {
71+
compatible = "microchip,pcie-host-1.0";
72+
reg = <0x0 0x70000000 0x0 0x08000000>,
73+
<0x0 0x43008000 0x0 0x00002000>,
74+
<0x0 0x4300a000 0x0 0x00002000>;
75+
reg-names = "cfg", "bridge", "ctrl";
76+
device_type = "pci";
77+
#address-cells = <3>;
6978
#size-cells = <2>;
70-
pcie0: pcie@2030000000 {
71-
compatible = "microchip,pcie-host-1.0";
72-
reg = <0x0 0x70000000 0x0 0x08000000>,
73-
<0x0 0x43008000 0x0 0x00002000>,
74-
<0x0 0x4300a000 0x0 0x00002000>;
75-
reg-names = "cfg", "bridge", "ctrl";
76-
device_type = "pci";
77-
#address-cells = <3>;
78-
#size-cells = <2>;
79-
#interrupt-cells = <1>;
80-
interrupts = <119>;
81-
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
82-
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
83-
<0 0 0 2 &pcie_intc0 1>,
84-
<0 0 0 3 &pcie_intc0 2>,
85-
<0 0 0 4 &pcie_intc0 3>;
86-
interrupt-parent = <&plic0>;
87-
msi-parent = <&pcie0>;
88-
msi-controller;
89-
bus-range = <0x00 0x7f>;
90-
ranges = <0x03000000 0x0 0x78000000 0x0 0x78000000 0x0 0x04000000>;
91-
pcie_intc0: interrupt-controller {
92-
#address-cells = <0>;
93-
#interrupt-cells = <1>;
94-
interrupt-controller;
95-
};
79+
#interrupt-cells = <1>;
80+
interrupts = <119>;
81+
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
82+
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
83+
<0 0 0 2 &pcie_intc0 1>,
84+
<0 0 0 3 &pcie_intc0 2>,
85+
<0 0 0 4 &pcie_intc0 3>;
86+
interrupt-parent = <&plic0>;
87+
msi-parent = <&pcie0>;
88+
msi-controller;
89+
bus-range = <0x00 0x7f>;
90+
ranges = <0x03000000 0x0 0x78000000 0x0 0x78000000 0x0 0x04000000>;
91+
pcie_intc0: interrupt-controller {
92+
#address-cells = <0>;
93+
#interrupt-cells = <1>;
94+
interrupt-controller;
9695
};
96+
};
9797
};

‎Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml‎

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -73,21 +73,21 @@ examples:
7373
#include <dt-bindings/interrupt-controller/arm-gic.h>
7474
#include <dt-bindings/power/r8a774c0-sysc.h>
7575
76-
pcie0_ep: pcie-ep@fe000000 {
77-
compatible = "renesas,r8a774c0-pcie-ep",
78-
"renesas,rcar-gen3-pcie-ep";
79-
reg = <0xfe000000 0x80000>,
80-
<0xfe100000 0x100000>,
81-
<0xfe200000 0x200000>,
82-
<0x30000000 0x8000000>,
83-
<0x38000000 0x8000000>;
84-
reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
85-
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
86-
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
87-
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
88-
resets = <&cpg 319>;
89-
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
90-
clocks = <&cpg CPG_MOD 319>;
91-
clock-names = "pcie";
92-
max-functions = /bits/ 8 <1>;
76+
pcie0_ep: pcie-ep@fe000000 {
77+
compatible = "renesas,r8a774c0-pcie-ep",
78+
"renesas,rcar-gen3-pcie-ep";
79+
reg = <0xfe000000 0x80000>,
80+
<0xfe100000 0x100000>,
81+
<0xfe200000 0x200000>,
82+
<0x30000000 0x8000000>,
83+
<0x38000000 0x8000000>;
84+
reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
85+
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
86+
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
87+
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
88+
resets = <&cpg 319>;
89+
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
90+
clocks = <&cpg CPG_MOD 319>;
91+
clock-names = "pcie";
92+
max-functions = /bits/ 8 <1>;
9393
};

‎Documentation/devicetree/bindings/pci/rcar-pci-host.yaml‎

Lines changed: 23 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -113,27 +113,27 @@ examples:
113113
pcie: pcie@fe000000 {
114114
compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
115115
reg = <0 0xfe000000 0 0x80000>;
116-
#address-cells = <3>;
117-
#size-cells = <2>;
118-
bus-range = <0x00 0xff>;
119-
device_type = "pci";
120-
ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
121-
<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
122-
<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
123-
<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
124-
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>,
125-
<0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
126-
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
127-
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
128-
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
129-
#interrupt-cells = <1>;
130-
interrupt-map-mask = <0 0 0 0>;
131-
interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
132-
clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
133-
clock-names = "pcie", "pcie_bus";
134-
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
135-
resets = <&cpg 319>;
136-
vpcie3v3-supply = <&pcie_3v3>;
137-
vpcie12v-supply = <&pcie_12v>;
138-
};
116+
#address-cells = <3>;
117+
#size-cells = <2>;
118+
bus-range = <0x00 0xff>;
119+
device_type = "pci";
120+
ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
121+
<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
122+
<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
123+
<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
124+
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>,
125+
<0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
126+
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
127+
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
128+
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
129+
#interrupt-cells = <1>;
130+
interrupt-map-mask = <0 0 0 0>;
131+
interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
132+
clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
133+
clock-names = "pcie", "pcie_bus";
134+
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
135+
resets = <&cpg 319>;
136+
vpcie3v3-supply = <&pcie_3v3>;
137+
vpcie12v-supply = <&pcie_12v>;
138+
};
139139
};

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