@@ -123,6 +123,44 @@ static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp
123123 }
124124}
125125
126+ static int psp_init_sriov_microcode (struct psp_context * psp )
127+ {
128+ struct amdgpu_device * adev = psp -> adev ;
129+ char ucode_prefix [30 ];
130+ int ret = 0 ;
131+
132+ amdgpu_ucode_ip_version_decode (adev , MP0_HWIP , ucode_prefix , sizeof (ucode_prefix ));
133+
134+ switch (adev -> ip_versions [MP0_HWIP ][0 ]) {
135+ case IP_VERSION (9 , 0 , 0 ):
136+ adev -> virt .autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2 ;
137+ ret = psp_init_cap_microcode (psp , ucode_prefix );
138+ break ;
139+ case IP_VERSION (11 , 0 , 9 ):
140+ adev -> virt .autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2 ;
141+ ret = psp_init_cap_microcode (psp , ucode_prefix );
142+ break ;
143+ case IP_VERSION (11 , 0 , 7 ):
144+ adev -> virt .autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2 ;
145+ ret = psp_init_cap_microcode (psp , ucode_prefix );
146+ break ;
147+ case IP_VERSION (13 , 0 , 2 ):
148+ adev -> virt .autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2 ;
149+ ret = psp_init_cap_microcode (psp , ucode_prefix );
150+ ret &= psp_init_ta_microcode (psp , ucode_prefix );
151+ break ;
152+ case IP_VERSION (13 , 0 , 0 ):
153+ adev -> virt .autoload_ucode_id = 0 ;
154+ break ;
155+ case IP_VERSION (13 , 0 , 10 ):
156+ adev -> virt .autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA ;
157+ break ;
158+ default :
159+ return - EINVAL ;
160+ }
161+ return ret ;
162+ }
163+
126164static int psp_early_init (void * handle )
127165{
128166 struct amdgpu_device * adev = (struct amdgpu_device * )handle ;
@@ -193,7 +231,10 @@ static int psp_early_init(void *handle)
193231
194232 psp_check_pmfw_centralized_cstate_management (psp );
195233
196- return 0 ;
234+ if (amdgpu_sriov_vf (adev ))
235+ return psp_init_sriov_microcode (psp );
236+ else
237+ return psp_init_microcode (psp );
197238}
198239
199240void psp_ta_free_shared_buf (struct ta_mem_context * mem_ctx )
@@ -351,42 +392,6 @@ static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
351392 return ret ;
352393}
353394
354- static int psp_init_sriov_microcode (struct psp_context * psp )
355- {
356- struct amdgpu_device * adev = psp -> adev ;
357- int ret = 0 ;
358-
359- switch (adev -> ip_versions [MP0_HWIP ][0 ]) {
360- case IP_VERSION (9 , 0 , 0 ):
361- adev -> virt .autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2 ;
362- ret = psp_init_cap_microcode (psp , "vega10" );
363- break ;
364- case IP_VERSION (11 , 0 , 9 ):
365- adev -> virt .autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2 ;
366- ret = psp_init_cap_microcode (psp , "navi12" );
367- break ;
368- case IP_VERSION (11 , 0 , 7 ):
369- adev -> virt .autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2 ;
370- ret = psp_init_cap_microcode (psp , "sienna_cichlid" );
371- break ;
372- case IP_VERSION (13 , 0 , 2 ):
373- adev -> virt .autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2 ;
374- ret = psp_init_cap_microcode (psp , "aldebaran" );
375- ret &= psp_init_ta_microcode (psp , "aldebaran" );
376- break ;
377- case IP_VERSION (13 , 0 , 0 ):
378- adev -> virt .autoload_ucode_id = 0 ;
379- break ;
380- case IP_VERSION (13 , 0 , 10 ):
381- adev -> virt .autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA ;
382- break ;
383- default :
384- ret = - EINVAL ;
385- break ;
386- }
387- return ret ;
388- }
389-
390395static int psp_sw_init (void * handle )
391396{
392397 struct amdgpu_device * adev = (struct amdgpu_device * )handle ;
@@ -402,15 +407,6 @@ static int psp_sw_init(void *handle)
402407 ret = - ENOMEM ;
403408 }
404409
405- if (amdgpu_sriov_vf (adev ))
406- ret = psp_init_sriov_microcode (psp );
407- else
408- ret = psp_init_microcode (psp );
409- if (ret ) {
410- DRM_ERROR ("Failed to load psp firmware!\n" );
411- return ret ;
412- }
413-
414410 adev -> psp .xgmi_context .supports_extended_data =
415411 !adev -> gmc .xgmi .connected_to_cpu &&
416412 adev -> ip_versions [MP0_HWIP ][0 ] == IP_VERSION (13 , 0 , 2 );
@@ -2914,19 +2910,13 @@ int psp_ring_cmd_submit(struct psp_context *psp,
29142910 return 0 ;
29152911}
29162912
2917- int psp_init_asd_microcode (struct psp_context * psp ,
2918- const char * chip_name )
2913+ int psp_init_asd_microcode (struct psp_context * psp , const char * chip_name )
29192914{
29202915 struct amdgpu_device * adev = psp -> adev ;
29212916 char fw_name [PSP_FW_NAME_LEN ];
29222917 const struct psp_firmware_header_v1_0 * asd_hdr ;
29232918 int err = 0 ;
29242919
2925- if (!chip_name ) {
2926- dev_err (adev -> dev , "invalid chip name for asd microcode\n" );
2927- return - EINVAL ;
2928- }
2929-
29302920 snprintf (fw_name , sizeof (fw_name ), "amdgpu/%s_asd.bin" , chip_name );
29312921 err = request_firmware (& adev -> psp .asd_fw , fw_name , adev -> dev );
29322922 if (err )
@@ -2950,19 +2940,13 @@ int psp_init_asd_microcode(struct psp_context *psp,
29502940 return err ;
29512941}
29522942
2953- int psp_init_toc_microcode (struct psp_context * psp ,
2954- const char * chip_name )
2943+ int psp_init_toc_microcode (struct psp_context * psp , const char * chip_name )
29552944{
29562945 struct amdgpu_device * adev = psp -> adev ;
29572946 char fw_name [PSP_FW_NAME_LEN ];
29582947 const struct psp_firmware_header_v1_0 * toc_hdr ;
29592948 int err = 0 ;
29602949
2961- if (!chip_name ) {
2962- dev_err (adev -> dev , "invalid chip name for toc microcode\n" );
2963- return - EINVAL ;
2964- }
2965-
29662950 snprintf (fw_name , sizeof (fw_name ), "amdgpu/%s_toc.bin" , chip_name );
29672951 err = request_firmware (& adev -> psp .toc_fw , fw_name , adev -> dev );
29682952 if (err )
@@ -3113,8 +3097,7 @@ static int psp_init_sos_base_fw(struct amdgpu_device *adev)
31133097 return 0 ;
31143098}
31153099
3116- int psp_init_sos_microcode (struct psp_context * psp ,
3117- const char * chip_name )
3100+ int psp_init_sos_microcode (struct psp_context * psp , const char * chip_name )
31183101{
31193102 struct amdgpu_device * adev = psp -> adev ;
31203103 char fw_name [PSP_FW_NAME_LEN ];
@@ -3127,11 +3110,6 @@ int psp_init_sos_microcode(struct psp_context *psp,
31273110 uint8_t * ucode_array_start_addr ;
31283111 int fw_index = 0 ;
31293112
3130- if (!chip_name ) {
3131- dev_err (adev -> dev , "invalid chip name for sos microcode\n" );
3132- return - EINVAL ;
3133- }
3134-
31353113 snprintf (fw_name , sizeof (fw_name ), "amdgpu/%s_sos.bin" , chip_name );
31363114 err = request_firmware (& adev -> psp .sos_fw , fw_name , adev -> dev );
31373115 if (err )
@@ -3398,20 +3376,14 @@ int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name)
33983376 return err ;
33993377}
34003378
3401- int psp_init_cap_microcode (struct psp_context * psp ,
3402- const char * chip_name )
3379+ int psp_init_cap_microcode (struct psp_context * psp , const char * chip_name )
34033380{
34043381 struct amdgpu_device * adev = psp -> adev ;
34053382 char fw_name [PSP_FW_NAME_LEN ];
34063383 const struct psp_firmware_header_v1_0 * cap_hdr_v1_0 ;
34073384 struct amdgpu_firmware_info * info = NULL ;
34083385 int err = 0 ;
34093386
3410- if (!chip_name ) {
3411- dev_err (adev -> dev , "invalid chip name for cap microcode\n" );
3412- return - EINVAL ;
3413- }
3414-
34153387 if (!amdgpu_sriov_vf (adev )) {
34163388 dev_err (adev -> dev , "cap microcode should only be loaded under SRIOV\n" );
34173389 return - EINVAL ;
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