@@ -1187,6 +1187,7 @@ static void esdhc_reset_tuning(struct sdhci_host *host)
11871187 struct sdhci_pltfm_host * pltfm_host = sdhci_priv (host );
11881188 struct pltfm_imx_data * imx_data = sdhci_pltfm_priv (pltfm_host );
11891189 u32 ctrl ;
1190+ int ret ;
11901191
11911192 /* Reset the tuning circuit */
11921193 if (esdhc_is_usdhc (imx_data )) {
@@ -1199,7 +1200,22 @@ static void esdhc_reset_tuning(struct sdhci_host *host)
11991200 } else if (imx_data -> socdata -> flags & ESDHC_FLAG_STD_TUNING ) {
12001201 ctrl = readl (host -> ioaddr + SDHCI_AUTO_CMD_STATUS );
12011202 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL ;
1203+ ctrl &= ~ESDHC_MIX_CTRL_EXE_TUNE ;
12021204 writel (ctrl , host -> ioaddr + SDHCI_AUTO_CMD_STATUS );
1205+ /* Make sure ESDHC_MIX_CTRL_EXE_TUNE cleared */
1206+ ret = readl_poll_timeout (host -> ioaddr + SDHCI_AUTO_CMD_STATUS ,
1207+ ctrl , !(ctrl & ESDHC_MIX_CTRL_EXE_TUNE ), 1 , 50 );
1208+ if (ret == - ETIMEDOUT )
1209+ dev_warn (mmc_dev (host -> mmc ),
1210+ "Warning! clear execute tuning bit failed\n" );
1211+ /*
1212+ * SDHCI_INT_DATA_AVAIL is W1C bit, set this bit will clear the
1213+ * usdhc IP internal logic flag execute_tuning_with_clr_buf, which
1214+ * will finally make sure the normal data transfer logic correct.
1215+ */
1216+ ctrl = readl (host -> ioaddr + SDHCI_INT_STATUS );
1217+ ctrl |= SDHCI_INT_DATA_AVAIL ;
1218+ writel (ctrl , host -> ioaddr + SDHCI_INT_STATUS );
12031219 }
12041220 }
12051221}
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