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Merge branch 'pci/controller/microchip'
- Move PLDA XpressRICH generic DT binding properties to plda,xpressrich3-axi-common.yaml where they can be shared across PLDA-based drivers (Minda Chen) - Create a drivers/pci/controller/plda/ directory for PLDA-based drivers and move pcie-microchip-host.c there (Minda Chen) - Move PLDA generic macros to pcie-plda.h where they can be shared across drivers (Minda Chen) - Extract PLDA generic structures from pcie-microchip-host.c, rename them to be generic, and move them to pcie-plda-host.c where they can be shared across drivers (Minda Chen) - Add a .request_event_irq() callback for requesting device-specific interrupts in addition to PLDA-generic interrupts (Minda Chen) - Add DT binding and driver for the StarFive JH7110 SoC, based on PLDA IP (Minda Chen) * pci/controller/microchip: PCI: starfive: Add JH7110 PCIe controller dt-bindings: PCI: Add StarFive JH7110 PCIe controller PCI: Add PCIE_RESET_CONFIG_DEVICE_WAIT_MS waiting time value PCI: plda: Pass pci_host_bridge to plda_pcie_setup_iomems() PCI: plda: Add host init/deinit and map bus functions PCI: plda: Add event bitmap field to struct plda_pcie_rp PCI: microchip: Move IRQ functions to pcie-plda-host.c PCI: microchip: Add event irqchip field to host port and add PLDA irqchip PCI: microchip: Add get_events() callback and PLDA get_event() PCI: microchip: Add INTx and MSI event num to struct plda_event PCI: microchip: Add request_event_irq() callback function PCI: microchip: Add num_events field to struct plda_pcie_rp PCI: microchip: Rename interrupt related functions PCI: microchip: Move PLDA functions to pcie-plda-host.c PCI: microchip: Rename PLDA functions to be generic PCI: microchip: Move PLDA structures to plda-pcie.h PCI: microchip: Rename PLDA structures to be generic PCI: microchip: Add bridge_addr field to struct mc_pcie PCI: microchip: Move PLDA IP register macros to pcie-plda.h PCI: microchip: Move pcie-microchip-host.c to PLDA directory dt-bindings: PCI: Add PLDA XpressRICH PCIe host common properties # Conflicts: # drivers/pci/pci.h
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‎Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml‎

Lines changed: 1 addition & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -10,21 +10,13 @@ maintainers:
1010
- Daire McNamara <daire.mcnamara@microchip.com>
1111

1212
allOf:
13-
- $ref: /schemas/pci/pci-host-bridge.yaml#
13+
- $ref: plda,xpressrich3-axi-common.yaml#
1414
- $ref: /schemas/interrupt-controller/msi-controller.yaml#
1515

1616
properties:
1717
compatible:
1818
const: microchip,pcie-host-1.0 # PolarFire
1919

20-
reg:
21-
maxItems: 2
22-
23-
reg-names:
24-
items:
25-
- const: cfg
26-
- const: apb
27-
2820
clocks:
2921
description:
3022
Fabric Interface Controllers, FICs, are the interface between the FPGA
@@ -52,18 +44,6 @@ properties:
5244
items:
5345
pattern: '^fic[0-3]$'
5446

55-
interrupts:
56-
minItems: 1
57-
items:
58-
- description: PCIe host controller
59-
- description: builtin MSI controller
60-
61-
interrupt-names:
62-
minItems: 1
63-
items:
64-
- const: pcie
65-
- const: msi
66-
6747
ranges:
6848
minItems: 1
6949
maxItems: 3
@@ -72,39 +52,6 @@ properties:
7252
minItems: 1
7353
maxItems: 6
7454

75-
msi-controller:
76-
description: Identifies the node as an MSI controller.
77-
78-
msi-parent:
79-
description: MSI controller the device is capable of using.
80-
81-
interrupt-controller:
82-
type: object
83-
properties:
84-
'#address-cells':
85-
const: 0
86-
87-
'#interrupt-cells':
88-
const: 1
89-
90-
interrupt-controller: true
91-
92-
required:
93-
- '#address-cells'
94-
- '#interrupt-cells'
95-
- interrupt-controller
96-
97-
additionalProperties: false
98-
99-
required:
100-
- reg
101-
- reg-names
102-
- "#interrupt-cells"
103-
- interrupts
104-
- interrupt-map-mask
105-
- interrupt-map
106-
- msi-controller
107-
10855
unevaluatedProperties: false
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examples:

‎Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml‎

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@@ -0,0 +1,75 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/pci/plda,xpressrich3-axi-common.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: PLDA XpressRICH PCIe host common properties
8+
9+
maintainers:
10+
- Daire McNamara <daire.mcnamara@microchip.com>
11+
- Kevin Xie <kevin.xie@starfivetech.com>
12+
13+
description:
14+
Generic PLDA XpressRICH PCIe host common properties.
15+
16+
allOf:
17+
- $ref: /schemas/pci/pci-host-bridge.yaml#
18+
19+
properties:
20+
reg:
21+
maxItems: 2
22+
23+
reg-names:
24+
items:
25+
- const: cfg
26+
- const: apb
27+
28+
interrupts:
29+
minItems: 1
30+
items:
31+
- description: PCIe host controller
32+
- description: builtin MSI controller
33+
34+
interrupt-names:
35+
minItems: 1
36+
items:
37+
- const: pcie
38+
- const: msi
39+
40+
msi-controller:
41+
description: Identifies the node as an MSI controller.
42+
43+
msi-parent:
44+
description: MSI controller the device is capable of using.
45+
46+
interrupt-controller:
47+
type: object
48+
properties:
49+
'#address-cells':
50+
const: 0
51+
52+
'#interrupt-cells':
53+
const: 1
54+
55+
interrupt-controller: true
56+
57+
required:
58+
- '#address-cells'
59+
- '#interrupt-cells'
60+
- interrupt-controller
61+
62+
additionalProperties: false
63+
64+
required:
65+
- reg
66+
- reg-names
67+
- interrupts
68+
- msi-controller
69+
- "#interrupt-cells"
70+
- interrupt-map-mask
71+
- interrupt-map
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73+
additionalProperties: true
74+
75+
...

‎Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml‎

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1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/pci/starfive,jh7110-pcie.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: StarFive JH7110 PCIe host controller
8+
9+
maintainers:
10+
- Kevin Xie <kevin.xie@starfivetech.com>
11+
12+
allOf:
13+
- $ref: plda,xpressrich3-axi-common.yaml#
14+
15+
properties:
16+
compatible:
17+
const: starfive,jh7110-pcie
18+
19+
clocks:
20+
items:
21+
- description: NOC bus clock
22+
- description: Transport layer clock
23+
- description: AXI MST0 clock
24+
- description: APB clock
25+
26+
clock-names:
27+
items:
28+
- const: noc
29+
- const: tl
30+
- const: axi_mst0
31+
- const: apb
32+
33+
resets:
34+
items:
35+
- description: AXI MST0 reset
36+
- description: AXI SLAVE0 reset
37+
- description: AXI SLAVE reset
38+
- description: PCIE BRIDGE reset
39+
- description: PCIE CORE reset
40+
- description: PCIE APB reset
41+
42+
reset-names:
43+
items:
44+
- const: mst0
45+
- const: slv0
46+
- const: slv
47+
- const: brg
48+
- const: core
49+
- const: apb
50+
51+
starfive,stg-syscon:
52+
$ref: /schemas/types.yaml#/definitions/phandle-array
53+
description:
54+
The phandle to System Register Controller syscon node.
55+
56+
perst-gpios:
57+
description: GPIO controlled connection to PERST# signal
58+
maxItems: 1
59+
60+
phys:
61+
description:
62+
Specified PHY is attached to PCIe controller.
63+
maxItems: 1
64+
65+
required:
66+
- clocks
67+
- resets
68+
- starfive,stg-syscon
69+
70+
unevaluatedProperties: false
71+
72+
examples:
73+
- |
74+
#include <dt-bindings/gpio/gpio.h>
75+
soc {
76+
#address-cells = <2>;
77+
#size-cells = <2>;
78+
79+
pcie@940000000 {
80+
compatible = "starfive,jh7110-pcie";
81+
reg = <0x9 0x40000000 0x0 0x10000000>,
82+
<0x0 0x2b000000 0x0 0x1000000>;
83+
reg-names = "cfg", "apb";
84+
#address-cells = <3>;
85+
#size-cells = <2>;
86+
#interrupt-cells = <1>;
87+
device_type = "pci";
88+
ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
89+
<0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
90+
starfive,stg-syscon = <&stg_syscon>;
91+
bus-range = <0x0 0xff>;
92+
interrupt-parent = <&plic>;
93+
interrupts = <56>;
94+
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
95+
interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
96+
<0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
97+
<0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
98+
<0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
99+
msi-controller;
100+
clocks = <&syscrg 86>,
101+
<&stgcrg 10>,
102+
<&stgcrg 8>,
103+
<&stgcrg 9>;
104+
clock-names = "noc", "tl", "axi_mst0", "apb";
105+
resets = <&stgcrg 11>,
106+
<&stgcrg 12>,
107+
<&stgcrg 13>,
108+
<&stgcrg 14>,
109+
<&stgcrg 15>,
110+
<&stgcrg 16>;
111+
perst-gpios = <&gpios 26 GPIO_ACTIVE_LOW>;
112+
phys = <&pciephy0>;
113+
114+
pcie_intc0: interrupt-controller {
115+
#address-cells = <0>;
116+
#interrupt-cells = <1>;
117+
interrupt-controller;
118+
};
119+
};
120+
};

‎MAINTAINERS‎

Lines changed: 17 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -17219,6 +17219,14 @@ S: Maintained
1721917219
F: Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt
1722017220
F: drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c
1722117221

17222+
PCI DRIVER FOR PLDA PCIE IP
17223+
M: Daire McNamara <daire.mcnamara@microchip.com>
17224+
L: linux-pci@vger.kernel.org
17225+
S: Maintained
17226+
F: Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml
17227+
F: drivers/pci/controller/plda/pcie-plda-host.c
17228+
F: drivers/pci/controller/plda/pcie-plda.h
17229+
1722217230
PCI DRIVER FOR RENESAS R-CAR
1722317231
M: Marek Vasut <marek.vasut+renesas@gmail.com>
1722417232
M: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
@@ -17449,7 +17457,7 @@ M: Daire McNamara <daire.mcnamara@microchip.com>
1744917457
L: linux-pci@vger.kernel.org
1745017458
S: Supported
1745117459
F: Documentation/devicetree/bindings/pci/microchip*
17452-
F: drivers/pci/controller/*microchip*
17460+
F: drivers/pci/controller/plda/*microchip*
1745317461

1745417462
PCIE DRIVER FOR QUALCOMM MSM
1745517463
M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
@@ -17479,6 +17487,13 @@ L: linux-pci@vger.kernel.org
1747917487
S: Maintained
1748017488
F: drivers/pci/controller/dwc/*spear*
1748117489

17490+
PCIE DRIVER FOR STARFIVE JH71x0
17491+
M: Kevin Xie <kevin.xie@starfivetech.com>
17492+
L: linux-pci@vger.kernel.org
17493+
S: Maintained
17494+
F: Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
17495+
F: drivers/pci/controller/plda/pcie-starfive.c
17496+
1748217497
PCIE ENDPOINT DRIVER FOR QUALCOMM
1748317498
M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
1748417499
L: linux-pci@vger.kernel.org
@@ -19285,7 +19300,7 @@ F: drivers/clk/microchip/clk-mpfs*.c
1928519300
F: drivers/firmware/microchip/mpfs-auto-update.c
1928619301
F: drivers/i2c/busses/i2c-microchip-corei2c.c
1928719302
F: drivers/mailbox/mailbox-mpfs.c
19288-
F: drivers/pci/controller/pcie-microchip-host.c
19303+
F: drivers/pci/controller/plda/pcie-microchip-host.c
1928919304
F: drivers/pwm/pwm-microchip-core.c
1929019305
F: drivers/reset/reset-mpfs.c
1929119306
F: drivers/rtc/rtc-mpfs.c

‎drivers/pci/controller/Kconfig‎

Lines changed: 1 addition & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -215,14 +215,6 @@ config PCIE_MT7621
215215
help
216216
This selects a driver for the MediaTek MT7621 PCIe Controller.
217217

218-
config PCIE_MICROCHIP_HOST
219-
tristate "Microchip AXI PCIe controller"
220-
depends on PCI_MSI && OF
221-
select PCI_HOST_COMMON
222-
help
223-
Say Y here if you want kernel to support the Microchip AXI PCIe
224-
Host Bridge driver.
225-
226218
config PCI_HYPERV_INTERFACE
227219
tristate "Microsoft Hyper-V PCI Interface"
228220
depends on ((X86 && X86_64) || ARM64) && HYPERV && PCI_MSI
@@ -356,4 +348,5 @@ config PCIE_XILINX_CPM
356348
source "drivers/pci/controller/cadence/Kconfig"
357349
source "drivers/pci/controller/dwc/Kconfig"
358350
source "drivers/pci/controller/mobiveil/Kconfig"
351+
source "drivers/pci/controller/plda/Kconfig"
359352
endmenu

‎drivers/pci/controller/Makefile‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,6 @@ obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o
3333
obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
3434
obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
3535
obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o
36-
obj-$(CONFIG_PCIE_MICROCHIP_HOST) += pcie-microchip-host.o
3736
obj-$(CONFIG_VMD) += vmd.o
3837
obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
3938
obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
@@ -44,6 +43,7 @@ obj-$(CONFIG_PCIE_MT7621) += pcie-mt7621.o
4443
# pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
4544
obj-y += dwc/
4645
obj-y += mobiveil/
46+
obj-y += plda/
4747

4848

4949
# The following drivers are for devices that use the generic ACPI

‎drivers/pci/controller/plda/Kconfig‎

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1+
# SPDX-License-Identifier: GPL-2.0
2+
3+
menu "PLDA-based PCIe controllers"
4+
depends on PCI
5+
6+
config PCIE_PLDA_HOST
7+
bool
8+
9+
config PCIE_MICROCHIP_HOST
10+
tristate "Microchip AXI PCIe controller"
11+
depends on PCI_MSI && OF
12+
select PCI_HOST_COMMON
13+
select PCIE_PLDA_HOST
14+
help
15+
Say Y here if you want kernel to support the Microchip AXI PCIe
16+
Host Bridge driver.
17+
18+
config PCIE_STARFIVE_HOST
19+
tristate "StarFive PCIe host controller"
20+
depends on PCI_MSI && OF
21+
depends on ARCH_STARFIVE || COMPILE_TEST
22+
select PCIE_PLDA_HOST
23+
help
24+
Say Y here if you want to support the StarFive PCIe controller in
25+
host mode. StarFive PCIe controller uses PLDA PCIe core.
26+
27+
If you choose to build this driver as module it will be dynamically
28+
linked and module will be called pcie-starfive.ko.
29+
30+
endmenu

‎drivers/pci/controller/plda/Makefile‎

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@@ -0,0 +1,4 @@
1+
# SPDX-License-Identifier: GPL-2.0
2+
obj-$(CONFIG_PCIE_PLDA_HOST) += pcie-plda-host.o
3+
obj-$(CONFIG_PCIE_MICROCHIP_HOST) += pcie-microchip-host.o
4+
obj-$(CONFIG_PCIE_STARFIVE_HOST) += pcie-starfive.o

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