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dt-bindings: Improve phandle-array schemas
The 'phandle-array' type is a bit ambiguous. It can be either just an array of phandles or an array of phandles plus args. Many schemas for phandle-array properties aren't clear in the schema which case applies though the description usually describes it. The array of phandles case boils down to needing: items: maxItems: 1 The phandle plus args cases should typically take this form: items: - items: - description: A phandle - description: 1st arg cell - description: 2nd arg cell With this change, some examples need updating so that the bracketing of property values matches the schema. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Vinod Koul <vkoul@kernel.org> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Georgi Djakov <djakov@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> Link: https://lore.kernel.org/r/20220119015038.2433585-1-robh@kernel.org
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‎Documentation/devicetree/bindings/arm/cpus.yaml‎

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@@ -243,6 +243,8 @@ properties:
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cpu-idle-states:
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$ref: '/schemas/types.yaml#/definitions/phandle-array'
246+
items:
247+
maxItems: 1
246248
description: |
247249
List of phandles to idle state nodes supported
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by this cpu (see ./idle-states.yaml).

‎Documentation/devicetree/bindings/arm/idle-states.yaml‎

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@@ -337,143 +337,143 @@ examples:
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compatible = "arm,cortex-a57";
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reg = <0x0 0x0>;
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enable-method = "psci";
340-
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
341-
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
340+
cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
341+
<&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
342342
};
343343
344344
cpu@1 {
345345
device_type = "cpu";
346346
compatible = "arm,cortex-a57";
347347
reg = <0x0 0x1>;
348348
enable-method = "psci";
349-
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
350-
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
349+
cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
350+
<&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
351351
};
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353353
cpu@100 {
354354
device_type = "cpu";
355355
compatible = "arm,cortex-a57";
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reg = <0x0 0x100>;
357357
enable-method = "psci";
358-
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
359-
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
358+
cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
359+
<&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
360360
};
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cpu@101 {
363363
device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x101>;
366366
enable-method = "psci";
367-
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
368-
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
367+
cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
368+
<&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
369369
};
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cpu@10000 {
372372
device_type = "cpu";
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compatible = "arm,cortex-a57";
374374
reg = <0x0 0x10000>;
375375
enable-method = "psci";
376-
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
377-
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
376+
cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
377+
<&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
378378
};
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cpu@10001 {
381381
device_type = "cpu";
382382
compatible = "arm,cortex-a57";
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reg = <0x0 0x10001>;
384384
enable-method = "psci";
385-
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
386-
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
385+
cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
386+
<&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
387387
};
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389389
cpu@10100 {
390390
device_type = "cpu";
391391
compatible = "arm,cortex-a57";
392392
reg = <0x0 0x10100>;
393393
enable-method = "psci";
394-
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
395-
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
394+
cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
395+
<&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
396396
};
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398398
cpu@10101 {
399399
device_type = "cpu";
400400
compatible = "arm,cortex-a57";
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reg = <0x0 0x10101>;
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enable-method = "psci";
403-
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
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&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
403+
cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
404+
<&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
405405
};
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cpu@100000000 {
408408
device_type = "cpu";
409409
compatible = "arm,cortex-a53";
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reg = <0x1 0x0>;
411411
enable-method = "psci";
412-
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
413-
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
412+
cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
413+
<&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
414414
};
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cpu@100000001 {
417417
device_type = "cpu";
418418
compatible = "arm,cortex-a53";
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reg = <0x1 0x1>;
420420
enable-method = "psci";
421-
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
422-
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
421+
cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
422+
<&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
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};
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cpu@100000100 {
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device_type = "cpu";
427427
compatible = "arm,cortex-a53";
428428
reg = <0x1 0x100>;
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enable-method = "psci";
430-
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
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&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
430+
cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
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<&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
432432
};
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cpu@100000101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1 0x101>;
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enable-method = "psci";
439-
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
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&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
439+
cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
440+
<&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
441441
};
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cpu@100010000 {
444444
device_type = "cpu";
445445
compatible = "arm,cortex-a53";
446446
reg = <0x1 0x10000>;
447447
enable-method = "psci";
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cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
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&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
448+
cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
449+
<&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
450450
};
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cpu@100010001 {
453453
device_type = "cpu";
454454
compatible = "arm,cortex-a53";
455455
reg = <0x1 0x10001>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
458-
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
457+
cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
458+
<&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
459459
};
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cpu@100010100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
464464
reg = <0x1 0x10100>;
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enable-method = "psci";
466-
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
467-
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
466+
cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
467+
<&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
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};
469469
470470
cpu@100010101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1 0x10101>;
474474
enable-method = "psci";
475-
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
476-
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
475+
cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
476+
<&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
477477
};
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idle-states {
@@ -567,56 +567,56 @@ examples:
567567
device_type = "cpu";
568568
compatible = "arm,cortex-a15";
569569
reg = <0x0>;
570-
cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>;
570+
cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
571571
};
572572
573573
cpu@1 {
574574
device_type = "cpu";
575575
compatible = "arm,cortex-a15";
576576
reg = <0x1>;
577-
cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>;
577+
cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
578578
};
579579
580580
cpu@2 {
581581
device_type = "cpu";
582582
compatible = "arm,cortex-a15";
583583
reg = <0x2>;
584-
cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>;
584+
cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
585585
};
586586
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cpu@3 {
588588
device_type = "cpu";
589589
compatible = "arm,cortex-a15";
590590
reg = <0x3>;
591-
cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>;
591+
cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
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};
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594594
cpu@100 {
595595
device_type = "cpu";
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compatible = "arm,cortex-a7";
597597
reg = <0x100>;
598-
cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>;
598+
cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
599599
};
600600
601601
cpu@101 {
602602
device_type = "cpu";
603603
compatible = "arm,cortex-a7";
604604
reg = <0x101>;
605-
cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>;
605+
cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
606606
};
607607
608608
cpu@102 {
609609
device_type = "cpu";
610610
compatible = "arm,cortex-a7";
611611
reg = <0x102>;
612-
cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>;
612+
cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
613613
};
614614
615615
cpu@103 {
616616
device_type = "cpu";
617617
compatible = "arm,cortex-a7";
618618
reg = <0x103>;
619-
cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>;
619+
cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
620620
};
621621
622622
idle-states {

‎Documentation/devicetree/bindings/arm/pmu.yaml‎

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6767
interrupt-affinity:
6868
$ref: /schemas/types.yaml#/definitions/phandle-array
69+
items:
70+
maxItems: 1
6971
description:
7072
When using SPIs, specifies a list of phandles to CPU
7173
nodes corresponding directly to the affinity of

‎Documentation/devicetree/bindings/ata/sata_highbank.yaml‎

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@@ -51,6 +51,9 @@ properties:
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$ref: /schemas/types.yaml#/definitions/phandle-array
5252
minItems: 1
5353
maxItems: 8
54+
items:
55+
minItems: 2
56+
maxItems: 2
5457

5558
calxeda,tx-atten:
5659
description: |

‎Documentation/devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml‎

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@@ -35,7 +35,10 @@ properties:
3535
The SRAM that needs to be claimed to access the display engine
3636
bus.
3737
$ref: /schemas/types.yaml#/definitions/phandle-array
38-
maxItems: 1
38+
items:
39+
- items:
40+
- description: phandle to SRAM
41+
- description: register value for device
3942

4043
ranges: true
4144

‎Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml‎

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@@ -22,19 +22,28 @@ properties:
2222

2323
intel,npe-handle:
2424
$ref: '/schemas/types.yaml#/definitions/phandle-array'
25-
maxItems: 1
25+
items:
26+
- items:
27+
- description: phandle to the NPE this crypto engine
28+
- description: the NPE instance number
2629
description: phandle to the NPE this crypto engine is using, the cell
2730
describing the NPE instance to be used.
2831

2932
queue-rx:
3033
$ref: /schemas/types.yaml#/definitions/phandle-array
31-
maxItems: 1
34+
items:
35+
- items:
36+
- description: phandle to the RX queue on the NPE
37+
- description: the queue instance number
3238
description: phandle to the RX queue on the NPE, the cell describing
3339
the queue instance to be used.
3440

3541
queue-txready:
3642
$ref: /schemas/types.yaml#/definitions/phandle-array
37-
maxItems: 1
43+
items:
44+
- items:
45+
- description: phandle to the TX READY queue on the NPE
46+
- description: the queue instance number
3847
description: phandle to the TX READY queue on the NPE, the cell describing
3948
the queue instance to be used.
4049

‎Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-engine.yaml‎

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@@ -69,6 +69,8 @@ properties:
6969
$ref: /schemas/types.yaml#/definitions/phandle-array
7070
minItems: 1
7171
maxItems: 2
72+
items:
73+
maxItems: 1
7274
description: |
7375
Available display engine frontends (DE 1.0) or mixers (DE
7476
2.0/3.0) available.

‎Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -51,7 +51,10 @@ properties:
5151

5252
mediatek,syscon-hdmi:
5353
$ref: '/schemas/types.yaml#/definitions/phandle-array'
54-
maxItems: 1
54+
items:
55+
- items:
56+
- description: phandle to system configuration registers
57+
- description: register offset in the system configuration registers
5558
description: |
5659
phandle link and register offset to the system configuration registers.
5760

‎Documentation/devicetree/bindings/display/msm/gpu.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -64,6 +64,8 @@ properties:
6464
$ref: /schemas/types.yaml#/definitions/phandle-array
6565
minItems: 1
6666
maxItems: 4
67+
items:
68+
maxItems: 1
6769
description: |
6870
phandles to one or more reserved on-chip SRAM regions.
6971
phandle to the On Chip Memory (OCMEM) that's present on some a3xx and

‎Documentation/devicetree/bindings/display/renesas,du.yaml‎

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@@ -76,17 +76,21 @@ properties:
7676

7777
renesas,cmms:
7878
$ref: "/schemas/types.yaml#/definitions/phandle-array"
79+
items:
80+
maxItems: 1
7981
description:
8082
A list of phandles to the CMM instances present in the SoC, one for each
8183
available DU channel.
8284

8385
renesas,vsps:
8486
$ref: "/schemas/types.yaml#/definitions/phandle-array"
87+
items:
88+
items:
89+
- description: phandle to VSP instance that serves the DU channel
90+
- description: Channel index identifying the LIF instance in that VSP
8591
description:
8692
A list of phandle and channel index tuples to the VSPs that handle the
87-
memory interfaces for the DU channels. The phandle identifies the VSP
88-
instance that serves the DU channel, and the channel index identifies
89-
the LIF instance in that VSP.
93+
memory interfaces for the DU channels.
9094

9195
required:
9296
- compatible

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