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SruChallaherbertx
SruChalla
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herbertx
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crypto: octeontx2 - load microcode and create engine groups
CPT includes microcoded GigaCypher symmetric engines(SEs), IPsec symmetric engines(IEs), and asymmetric engines (AEs). Each engine receives CPT instructions from the engine groups it has subscribed to. This patch loads microcode, configures three engine groups(one for SEs, one for IEs and one for AEs), and configures all engines. Signed-off-by: Suheil Chandran <schandran@marvell.com> Signed-off-by: Lukasz Bartosik <lbartosik@marvell.com> Signed-off-by: Srujana Challa <schalla@marvell.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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8 files changed

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‎drivers/crypto/marvell/octeontx2/Makefile‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,6 @@
22
obj-$(CONFIG_CRYPTO_DEV_OCTEONTX2_CPT) += octeontx2-cpt.o
33

44
octeontx2-cpt-objs := otx2_cptpf_main.o otx2_cptpf_mbox.o \
5-
otx2_cpt_mbox_common.o
5+
otx2_cpt_mbox_common.o otx2_cptpf_ucode.o
66

77
ccflags-y += -I$(srctree)/drivers/net/ethernet/marvell/octeontx2/af

‎drivers/crypto/marvell/octeontx2/otx2_cpt_common.h‎

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,37 @@
1818
#define OTX2_CPT_RVU_FUNC_ADDR_S(blk, slot, offs) \
1919
(((blk) << 20) | ((slot) << 12) | (offs))
2020

21+
#define OTX2_CPT_INVALID_CRYPTO_ENG_GRP 0xFF
22+
#define OTX2_CPT_NAME_LENGTH 64
23+
24+
#define BAD_OTX2_CPT_ENG_TYPE OTX2_CPT_MAX_ENG_TYPES
25+
26+
enum otx2_cpt_eng_type {
27+
OTX2_CPT_AE_TYPES = 1,
28+
OTX2_CPT_SE_TYPES = 2,
29+
OTX2_CPT_IE_TYPES = 3,
30+
OTX2_CPT_MAX_ENG_TYPES,
31+
};
32+
33+
/* Take mbox id from end of CPT mbox range in AF (range 0xA00 - 0xBFF) */
34+
#define MBOX_MSG_GET_ENG_GRP_NUM 0xBFF
35+
36+
/*
37+
* Message request and response to get engine group number
38+
* which has attached a given type of engines (SE, AE, IE)
39+
* This messages are only used between CPT PF <=> CPT VF
40+
*/
41+
struct otx2_cpt_egrp_num_msg {
42+
struct mbox_msghdr hdr;
43+
u8 eng_type;
44+
};
45+
46+
struct otx2_cpt_egrp_num_rsp {
47+
struct mbox_msghdr hdr;
48+
u8 eng_type;
49+
u8 eng_grp_num;
50+
};
51+
2152
static inline void otx2_cpt_write64(void __iomem *reg_base, u64 blk, u64 slot,
2253
u64 offs, u64 val)
2354
{
@@ -34,4 +65,15 @@ static inline u64 otx2_cpt_read64(void __iomem *reg_base, u64 blk, u64 slot,
3465

3566
int otx2_cpt_send_ready_msg(struct otx2_mbox *mbox, struct pci_dev *pdev);
3667
int otx2_cpt_send_mbox_msg(struct otx2_mbox *mbox, struct pci_dev *pdev);
68+
69+
int otx2_cpt_send_af_reg_requests(struct otx2_mbox *mbox,
70+
struct pci_dev *pdev);
71+
int otx2_cpt_add_read_af_reg(struct otx2_mbox *mbox,
72+
struct pci_dev *pdev, u64 reg, u64 *val);
73+
int otx2_cpt_add_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,
74+
u64 reg, u64 val);
75+
int otx2_cpt_read_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,
76+
u64 reg, u64 *val);
77+
int otx2_cpt_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,
78+
u64 reg, u64 val);
3779
#endif /* __OTX2_CPT_COMMON_H */

‎drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c‎

Lines changed: 77 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -35,3 +35,80 @@ int otx2_cpt_send_ready_msg(struct otx2_mbox *mbox, struct pci_dev *pdev)
3535

3636
return otx2_cpt_send_mbox_msg(mbox, pdev);
3737
}
38+
39+
int otx2_cpt_send_af_reg_requests(struct otx2_mbox *mbox, struct pci_dev *pdev)
40+
{
41+
return otx2_cpt_send_mbox_msg(mbox, pdev);
42+
}
43+
44+
int otx2_cpt_add_read_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,
45+
u64 reg, u64 *val)
46+
{
47+
struct cpt_rd_wr_reg_msg *reg_msg;
48+
49+
reg_msg = (struct cpt_rd_wr_reg_msg *)
50+
otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*reg_msg),
51+
sizeof(*reg_msg));
52+
if (reg_msg == NULL) {
53+
dev_err(&pdev->dev, "RVU MBOX failed to get message.\n");
54+
return -EFAULT;
55+
}
56+
57+
reg_msg->hdr.id = MBOX_MSG_CPT_RD_WR_REGISTER;
58+
reg_msg->hdr.sig = OTX2_MBOX_REQ_SIG;
59+
reg_msg->hdr.pcifunc = 0;
60+
61+
reg_msg->is_write = 0;
62+
reg_msg->reg_offset = reg;
63+
reg_msg->ret_val = val;
64+
65+
return 0;
66+
}
67+
68+
int otx2_cpt_add_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,
69+
u64 reg, u64 val)
70+
{
71+
struct cpt_rd_wr_reg_msg *reg_msg;
72+
73+
reg_msg = (struct cpt_rd_wr_reg_msg *)
74+
otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*reg_msg),
75+
sizeof(*reg_msg));
76+
if (reg_msg == NULL) {
77+
dev_err(&pdev->dev, "RVU MBOX failed to get message.\n");
78+
return -EFAULT;
79+
}
80+
81+
reg_msg->hdr.id = MBOX_MSG_CPT_RD_WR_REGISTER;
82+
reg_msg->hdr.sig = OTX2_MBOX_REQ_SIG;
83+
reg_msg->hdr.pcifunc = 0;
84+
85+
reg_msg->is_write = 1;
86+
reg_msg->reg_offset = reg;
87+
reg_msg->val = val;
88+
89+
return 0;
90+
}
91+
92+
int otx2_cpt_read_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,
93+
u64 reg, u64 *val)
94+
{
95+
int ret;
96+
97+
ret = otx2_cpt_add_read_af_reg(mbox, pdev, reg, val);
98+
if (ret)
99+
return ret;
100+
101+
return otx2_cpt_send_mbox_msg(mbox, pdev);
102+
}
103+
104+
int otx2_cpt_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,
105+
u64 reg, u64 val)
106+
{
107+
int ret;
108+
109+
ret = otx2_cpt_add_write_af_reg(mbox, pdev, reg, val);
110+
if (ret)
111+
return ret;
112+
113+
return otx2_cpt_send_mbox_msg(mbox, pdev);
114+
}

‎drivers/crypto/marvell/octeontx2/otx2_cptpf.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66
#define __OTX2_CPTPF_H
77

88
#include "otx2_cpt_common.h"
9+
#include "otx2_cptpf_ucode.h"
910

1011
struct otx2_cptpf_dev;
1112
struct otx2_cptvf_info {
@@ -27,6 +28,8 @@ struct otx2_cptpf_dev {
2728
void __iomem *vfpf_mbox_base; /* VF-PF mbox start address */
2829
struct pci_dev *pdev; /* PCI device handle */
2930
struct otx2_cptvf_info vf[OTX2_CPT_MAX_VFS_NUM];
31+
struct otx2_cpt_eng_grps eng_grps;/* Engine groups information */
32+
3033
/* AF <=> PF mbox */
3134
struct otx2_mbox afpf_mbox;
3235
struct work_struct afpf_mbox_work;

‎drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c‎

Lines changed: 72 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@
44
#include <linux/firmware.h>
55
#include "otx2_cpt_hw_types.h"
66
#include "otx2_cpt_common.h"
7+
#include "otx2_cptpf_ucode.h"
78
#include "otx2_cptpf.h"
89
#include "rvu_reg.h"
910

@@ -410,6 +411,59 @@ static int cpt_is_pf_usable(struct otx2_cptpf_dev *cptpf)
410411
return 0;
411412
}
412413

414+
static int cptpf_device_reset(struct otx2_cptpf_dev *cptpf)
415+
{
416+
int timeout = 10, ret;
417+
u64 reg = 0;
418+
419+
ret = otx2_cpt_write_af_reg(&cptpf->afpf_mbox, cptpf->pdev,
420+
CPT_AF_BLK_RST, 0x1);
421+
if (ret)
422+
return ret;
423+
424+
do {
425+
ret = otx2_cpt_read_af_reg(&cptpf->afpf_mbox, cptpf->pdev,
426+
CPT_AF_BLK_RST, &reg);
427+
if (ret)
428+
return ret;
429+
430+
if (!((reg >> 63) & 0x1))
431+
break;
432+
433+
usleep_range(10000, 20000);
434+
if (timeout-- < 0)
435+
return -EBUSY;
436+
} while (1);
437+
438+
return ret;
439+
}
440+
441+
static int cptpf_device_init(struct otx2_cptpf_dev *cptpf)
442+
{
443+
union otx2_cptx_af_constants1 af_cnsts1 = {0};
444+
int ret = 0;
445+
446+
/* Reset the CPT PF device */
447+
ret = cptpf_device_reset(cptpf);
448+
if (ret)
449+
return ret;
450+
451+
/* Get number of SE, IE and AE engines */
452+
ret = otx2_cpt_read_af_reg(&cptpf->afpf_mbox, cptpf->pdev,
453+
CPT_AF_CONSTANTS1, &af_cnsts1.u);
454+
if (ret)
455+
return ret;
456+
457+
cptpf->eng_grps.avail.max_se_cnt = af_cnsts1.s.se;
458+
cptpf->eng_grps.avail.max_ie_cnt = af_cnsts1.s.ie;
459+
cptpf->eng_grps.avail.max_ae_cnt = af_cnsts1.s.ae;
460+
461+
/* Disable all cores */
462+
ret = otx2_cpt_disable_all_cores(cptpf);
463+
464+
return ret;
465+
}
466+
413467
static int cptpf_sriov_disable(struct pci_dev *pdev)
414468
{
415469
struct otx2_cptpf_dev *cptpf = pci_get_drvdata(pdev);
@@ -446,6 +500,10 @@ static int cptpf_sriov_enable(struct pci_dev *pdev, int num_vfs)
446500
if (ret)
447501
goto destroy_flr;
448502

503+
ret = otx2_cpt_create_eng_grps(cptpf->pdev, &cptpf->eng_grps);
504+
if (ret)
505+
goto disable_intr;
506+
449507
cptpf->enabled_vfs = num_vfs;
450508
ret = pci_enable_sriov(pdev, num_vfs);
451509
if (ret)
@@ -543,8 +601,20 @@ static int otx2_cptpf_probe(struct pci_dev *pdev,
543601

544602
cptpf->max_vfs = pci_sriov_get_totalvfs(pdev);
545603

604+
/* Initialize CPT PF device */
605+
err = cptpf_device_init(cptpf);
606+
if (err)
607+
goto unregister_intr;
608+
609+
/* Initialize engine groups */
610+
err = otx2_cpt_init_eng_grps(pdev, &cptpf->eng_grps);
611+
if (err)
612+
goto unregister_intr;
613+
546614
return 0;
547615

616+
unregister_intr:
617+
cptpf_disable_afpf_mbox_intr(cptpf);
548618
destroy_afpf_mbox:
549619
cptpf_afpf_mbox_destroy(cptpf);
550620
clear_drvdata:
@@ -560,6 +630,8 @@ static void otx2_cptpf_remove(struct pci_dev *pdev)
560630
return;
561631

562632
cptpf_sriov_disable(pdev);
633+
/* Cleanup engine groups */
634+
otx2_cpt_cleanup_eng_grps(pdev, &cptpf->eng_grps);
563635
/* Disable AF-PF mailbox interrupt */
564636
cptpf_disable_afpf_mbox_intr(cptpf);
565637
/* Destroy AF-PF mbox */

‎drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c‎

Lines changed: 45 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -35,6 +35,29 @@ static int forward_to_af(struct otx2_cptpf_dev *cptpf,
3535
return 0;
3636
}
3737

38+
static int handle_msg_get_eng_grp_num(struct otx2_cptpf_dev *cptpf,
39+
struct otx2_cptvf_info *vf,
40+
struct mbox_msghdr *req)
41+
{
42+
struct otx2_cpt_egrp_num_msg *grp_req;
43+
struct otx2_cpt_egrp_num_rsp *rsp;
44+
45+
grp_req = (struct otx2_cpt_egrp_num_msg *)req;
46+
rsp = (struct otx2_cpt_egrp_num_rsp *)
47+
otx2_mbox_alloc_msg(&cptpf->vfpf_mbox, vf->vf_id, sizeof(*rsp));
48+
if (!rsp)
49+
return -ENOMEM;
50+
51+
rsp->hdr.id = MBOX_MSG_GET_ENG_GRP_NUM;
52+
rsp->hdr.sig = OTX2_MBOX_RSP_SIG;
53+
rsp->hdr.pcifunc = req->pcifunc;
54+
rsp->eng_type = grp_req->eng_type;
55+
rsp->eng_grp_num = otx2_cpt_get_eng_grp(&cptpf->eng_grps,
56+
grp_req->eng_type);
57+
58+
return 0;
59+
}
60+
3861
static int cptpf_handle_vf_req(struct otx2_cptpf_dev *cptpf,
3962
struct otx2_cptvf_info *vf,
4063
struct mbox_msghdr *req, int size)
@@ -45,7 +68,15 @@ static int cptpf_handle_vf_req(struct otx2_cptpf_dev *cptpf,
4568
if (req->sig != OTX2_MBOX_REQ_SIG)
4669
goto inval_msg;
4770

48-
return forward_to_af(cptpf, vf, req, size);
71+
switch (req->id) {
72+
case MBOX_MSG_GET_ENG_GRP_NUM:
73+
err = handle_msg_get_eng_grp_num(cptpf, vf, req);
74+
break;
75+
default:
76+
err = forward_to_af(cptpf, vf, req, size);
77+
break;
78+
}
79+
return err;
4980

5081
inval_msg:
5182
otx2_reply_invalid_msg(&cptpf->vfpf_mbox, vf->vf_id, 0, req->id);
@@ -148,6 +179,7 @@ static void process_afpf_mbox_msg(struct otx2_cptpf_dev *cptpf,
148179
struct mbox_msghdr *msg)
149180
{
150181
struct device *dev = &cptpf->pdev->dev;
182+
struct cpt_rd_wr_reg_msg *rsp_rd_wr;
151183

152184
if (msg->id >= MBOX_MSG_MAX) {
153185
dev_err(dev, "MBOX msg with unknown ID %d\n", msg->id);
@@ -164,6 +196,18 @@ static void process_afpf_mbox_msg(struct otx2_cptpf_dev *cptpf,
164196
cptpf->pf_id = (msg->pcifunc >> RVU_PFVF_PF_SHIFT) &
165197
RVU_PFVF_PF_MASK;
166198
break;
199+
case MBOX_MSG_CPT_RD_WR_REGISTER:
200+
rsp_rd_wr = (struct cpt_rd_wr_reg_msg *)msg;
201+
if (msg->rc) {
202+
dev_err(dev, "Reg %llx rd/wr(%d) failed %d\n",
203+
rsp_rd_wr->reg_offset, rsp_rd_wr->is_write,
204+
msg->rc);
205+
return;
206+
}
207+
if (!rsp_rd_wr->is_write)
208+
*rsp_rd_wr->ret_val = rsp_rd_wr->val;
209+
break;
210+
167211
default:
168212
dev_err(dev,
169213
"Unsupported msg %d received.\n", msg->id);

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