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drm/i915/psr: Do not trigger Frame Change events from frontbuffer flush
We want to get rid of triggering "Frame Change" events from frontbuffer flush calls. We are about to move using TRANS_PUSH register for this on LunarLake and onwards. Touching TRANS_PUSH register from fronbuffer flush would be problematic as it's written by DSB as well. Fix this by using intel_psr_exit when flush or invalidate is done on LunarLake and onwards. This is not possible on AlderLake and MeteorLake due to HW bug in PSR2 disable. This patch is also fixing problems with cursor plane where cursor is disappearing or duplicate cursor is seen on the screen. v2: Commit message updated Bspec: 68927, 68934, 66624 Reported-by: Janna Martl <janna.martl109@gmail.com> Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/5522 Fixes: 411ad63 ("drm/i915/psr: Use SFF_CTL on invalidate/flush for LunarLake onwards") Tested-by: Janna Martl <janna.martl109@gmail.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20250801062905.564453-1-jouni.hogander@intel.com
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drivers/gpu/drm/i915/display/intel_psr.c

Lines changed: 9 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -3254,7 +3254,9 @@ static void intel_psr_configure_full_frame_update(struct intel_dp *intel_dp)
32543254

32553255
static void _psr_invalidate_handle(struct intel_dp *intel_dp)
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{
3257-
if (intel_dp->psr.psr2_sel_fetch_enabled) {
3257+
struct intel_display *display = to_intel_display(intel_dp);
3258+
3259+
if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_enabled) {
32583260
if (!intel_dp->psr.psr2_sel_fetch_cff_enabled) {
32593261
intel_dp->psr.psr2_sel_fetch_cff_enabled = true;
32603262
intel_psr_configure_full_frame_update(intel_dp);
@@ -3340,7 +3342,7 @@ static void _psr_flush_handle(struct intel_dp *intel_dp)
33403342
{
33413343
struct intel_display *display = to_intel_display(intel_dp);
33423344

3343-
if (intel_dp->psr.psr2_sel_fetch_enabled) {
3345+
if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_enabled) {
33443346
if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {
33453347
/* can we turn CFF off? */
33463348
if (intel_dp->psr.busy_frontbuffer_bits == 0)
@@ -3357,11 +3359,13 @@ static void _psr_flush_handle(struct intel_dp *intel_dp)
33573359
* existing SU configuration
33583360
*/
33593361
intel_psr_configure_full_frame_update(intel_dp);
3360-
}
33613362

3362-
intel_psr_force_update(intel_dp);
3363+
intel_psr_force_update(intel_dp);
3364+
} else {
3365+
intel_psr_exit(intel_dp);
3366+
}
33633367

3364-
if (!intel_dp->psr.psr2_sel_fetch_enabled && !intel_dp->psr.active &&
3368+
if ((!intel_dp->psr.psr2_sel_fetch_enabled || DISPLAY_VER(display) >= 20) &&
33653369
!intel_dp->psr.busy_frontbuffer_bits)
33663370
queue_work(display->wq.unordered, &intel_dp->psr.work);
33673371
}

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