@@ -245,6 +245,48 @@ static struct irq_chip ks_pcie_msi_irq_chip = {
245245 .irq_unmask = ks_pcie_msi_unmask ,
246246};
247247
248+ /**
249+ * ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask registers
250+ * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone
251+ * PCIe host controller driver information.
252+ *
253+ * Since modification of dbi_cs2 involves different clock domain, read the
254+ * status back to ensure the transition is complete.
255+ */
256+ static void ks_pcie_set_dbi_mode (struct keystone_pcie * ks_pcie )
257+ {
258+ u32 val ;
259+
260+ val = ks_pcie_app_readl (ks_pcie , CMD_STATUS );
261+ val |= DBI_CS2 ;
262+ ks_pcie_app_writel (ks_pcie , CMD_STATUS , val );
263+
264+ do {
265+ val = ks_pcie_app_readl (ks_pcie , CMD_STATUS );
266+ } while (!(val & DBI_CS2 ));
267+ }
268+
269+ /**
270+ * ks_pcie_clear_dbi_mode() - Disable DBI mode
271+ * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone
272+ * PCIe host controller driver information.
273+ *
274+ * Since modification of dbi_cs2 involves different clock domain, read the
275+ * status back to ensure the transition is complete.
276+ */
277+ static void ks_pcie_clear_dbi_mode (struct keystone_pcie * ks_pcie )
278+ {
279+ u32 val ;
280+
281+ val = ks_pcie_app_readl (ks_pcie , CMD_STATUS );
282+ val &= ~DBI_CS2 ;
283+ ks_pcie_app_writel (ks_pcie , CMD_STATUS , val );
284+
285+ do {
286+ val = ks_pcie_app_readl (ks_pcie , CMD_STATUS );
287+ } while (val & DBI_CS2 );
288+ }
289+
248290static int ks_pcie_msi_host_init (struct dw_pcie_rp * pp )
249291{
250292 pp -> msi_irq_chip = & ks_pcie_msi_irq_chip ;
@@ -340,48 +382,6 @@ static const struct irq_domain_ops ks_pcie_intx_irq_domain_ops = {
340382 .xlate = irq_domain_xlate_onetwocell ,
341383};
342384
343- /**
344- * ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask registers
345- * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone
346- * PCIe host controller driver information.
347- *
348- * Since modification of dbi_cs2 involves different clock domain, read the
349- * status back to ensure the transition is complete.
350- */
351- static void ks_pcie_set_dbi_mode (struct keystone_pcie * ks_pcie )
352- {
353- u32 val ;
354-
355- val = ks_pcie_app_readl (ks_pcie , CMD_STATUS );
356- val |= DBI_CS2 ;
357- ks_pcie_app_writel (ks_pcie , CMD_STATUS , val );
358-
359- do {
360- val = ks_pcie_app_readl (ks_pcie , CMD_STATUS );
361- } while (!(val & DBI_CS2 ));
362- }
363-
364- /**
365- * ks_pcie_clear_dbi_mode() - Disable DBI mode
366- * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone
367- * PCIe host controller driver information.
368- *
369- * Since modification of dbi_cs2 involves different clock domain, read the
370- * status back to ensure the transition is complete.
371- */
372- static void ks_pcie_clear_dbi_mode (struct keystone_pcie * ks_pcie )
373- {
374- u32 val ;
375-
376- val = ks_pcie_app_readl (ks_pcie , CMD_STATUS );
377- val &= ~DBI_CS2 ;
378- ks_pcie_app_writel (ks_pcie , CMD_STATUS , val );
379-
380- do {
381- val = ks_pcie_app_readl (ks_pcie , CMD_STATUS );
382- } while (val & DBI_CS2 );
383- }
384-
385385static void ks_pcie_setup_rc_app_regs (struct keystone_pcie * ks_pcie )
386386{
387387 u32 val ;
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