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crypto: qat - generate dynamically arbiter mappings
The thread-to-arbiter mapping describes which arbiter can assign jobs to an acceleration engine thread. The existing mappings are functionally correct, but hardcoded and not optimized. Replace the static mappings with an algorithm that generates optimal mappings, based on the loaded configuration. The logic has been made common so that it can be shared between all QAT GEN4 devices. Signed-off-by: Damian Muszynski <damian.muszynski@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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-112
lines changed

5 files changed

+235
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‎drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c‎

Lines changed: 52 additions & 79 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,10 @@
2525
#define ADF_AE_GROUP_3 GENMASK(15, 12)
2626
#define ADF_AE_GROUP_4 BIT(16)
2727

28+
#define ENA_THD_MASK_ASYM GENMASK(1, 0)
29+
#define ENA_THD_MASK_SYM GENMASK(3, 0)
30+
#define ENA_THD_MASK_DC GENMASK(1, 0)
31+
2832
static const char * const adf_420xx_fw_objs[] = {
2933
[ADF_FW_SYM_OBJ] = ADF_420XX_SYM_OBJ,
3034
[ADF_FW_ASYM_OBJ] = ADF_420XX_ASYM_OBJ,
@@ -83,62 +87,6 @@ static const struct adf_fw_config adf_fw_dcc_config[] = {
8387
{ADF_AE_GROUP_4, ADF_FW_ADMIN_OBJ},
8488
};
8589

86-
/* Worker thread to service arbiter mappings */
87-
static const u32 default_thrd_to_arb_map[ADF_420XX_MAX_ACCELENGINES] = {
88-
0x00000055, 0x00000055, 0x00000055, 0x00000055,
89-
0x0000AAAA, 0x0000AAAA, 0x0000AAAA, 0x0000AAAA,
90-
0x00000055, 0x00000055, 0x00000055, 0x00000055,
91-
0x0000AAAA, 0x0000AAAA, 0x0000AAAA, 0x0000AAAA,
92-
0x0
93-
};
94-
95-
static const u32 thrd_to_arb_map_asym[ADF_420XX_MAX_ACCELENGINES] = {
96-
0x000000FF, 0x000000FF, 0x000000FF, 0x000000FF,
97-
0x000000FF, 0x000000FF, 0x000000FF, 0x000000FF,
98-
0x000000FF, 0x000000FF, 0x000000FF, 0x000000FF,
99-
0x000000FF, 0x000000FF, 0x000000FF, 0x000000FF,
100-
0x0
101-
};
102-
103-
static const u32 thrd_to_arb_map_sym[ADF_420XX_MAX_ACCELENGINES] = {
104-
0x0000FFFF, 0x0000FFFF, 0x0000FFFF, 0x0000FFFF,
105-
0x0000FFFF, 0x0000FFFF, 0x0000FFFF, 0x0000FFFF,
106-
0x0000FFFF, 0x0000FFFF, 0x0000FFFF, 0x0000FFFF,
107-
0x0000FFFF, 0x0000FFFF, 0x0000FFFF, 0x0000FFFF,
108-
0x0
109-
};
110-
111-
static const u32 thrd_to_arb_map_asym_dc[ADF_420XX_MAX_ACCELENGINES] = {
112-
0x00000055, 0x00000055, 0x00000055, 0x00000055,
113-
0x000000AA, 0x000000AA, 0x000000AA, 0x000000AA,
114-
0x000000AA, 0x000000AA, 0x000000AA, 0x000000AA,
115-
0x000000AA, 0x000000AA, 0x000000AA, 0x000000AA,
116-
0x0
117-
};
118-
119-
static const u32 thrd_to_arb_map_sym_dc[ADF_420XX_MAX_ACCELENGINES] = {
120-
0x00000055, 0x00000055, 0x00000055, 0x00000055,
121-
0x0000AAAA, 0x0000AAAA, 0x0000AAAA, 0x0000AAAA,
122-
0x0000AAAA, 0x0000AAAA, 0x0000AAAA, 0x0000AAAA,
123-
0x00000000, 0x00000000, 0x00000000, 0x00000000,
124-
0x0
125-
};
126-
127-
static const u32 thrd_to_arb_map_dc[ADF_420XX_MAX_ACCELENGINES] = {
128-
0x000000FF, 0x000000FF, 0x000000FF, 0x000000FF,
129-
0x000000FF, 0x000000FF, 0x000000FF, 0x000000FF,
130-
0x00000000, 0x00000000, 0x00000000, 0x00000000,
131-
0x00000000, 0x00000000, 0x00000000, 0x00000000,
132-
0x0
133-
};
134-
135-
static const u32 thrd_to_arb_map_dcc[ADF_420XX_MAX_ACCELENGINES] = {
136-
0x00000000, 0x00000000, 0x00000000, 0x00000000,
137-
0x0000FFFF, 0x0000FFFF, 0x0000FFFF, 0x0000FFFF,
138-
0x00000000, 0x00000000, 0x00000000, 0x00000000,
139-
0x00000000, 0x00000000, 0x00000000, 0x00000000,
140-
0x0
141-
};
14290

14391
static struct adf_hw_device_class adf_420xx_class = {
14492
.name = ADF_420XX_DEVICE_NAME,
@@ -346,24 +294,11 @@ static u32 get_accel_cap(struct adf_accel_dev *accel_dev)
346294

347295
static const u32 *adf_get_arbiter_mapping(struct adf_accel_dev *accel_dev)
348296
{
349-
switch (adf_get_service_enabled(accel_dev)) {
350-
case SVC_ASYM:
351-
return thrd_to_arb_map_asym;
352-
case SVC_SYM:
353-
return thrd_to_arb_map_sym;
354-
case SVC_DC:
355-
return thrd_to_arb_map_dc;
356-
case SVC_DCC:
357-
return thrd_to_arb_map_dcc;
358-
case SVC_ASYM_DC:
359-
case SVC_DC_ASYM:
360-
return thrd_to_arb_map_asym_dc;
361-
case SVC_DC_SYM:
362-
case SVC_SYM_DC:
363-
return thrd_to_arb_map_sym_dc;
364-
default:
365-
return default_thrd_to_arb_map;
366-
}
297+
if (adf_gen4_init_thd2arb_map(accel_dev))
298+
dev_warn(&GET_DEV(accel_dev),
299+
"Generate of the thread to arbiter map failed");
300+
301+
return GET_HW_DATA(accel_dev)->thd_to_arb_map;
367302
}
368303

369304
static void adf_init_rl_data(struct adf_rl_hw_data *rl_data)
@@ -384,11 +319,47 @@ static void adf_init_rl_data(struct adf_rl_hw_data *rl_data)
384319
rl_data->scale_ref = ADF_420XX_RL_SLICE_REF;
385320
}
386321

387-
enum adf_rp_groups {
388-
RP_GROUP_0 = 0,
389-
RP_GROUP_1,
390-
RP_GROUP_COUNT
391-
};
322+
static int get_rp_group(struct adf_accel_dev *accel_dev, u32 ae_mask)
323+
{
324+
switch (ae_mask) {
325+
case ADF_AE_GROUP_0:
326+
return RP_GROUP_0;
327+
case ADF_AE_GROUP_1:
328+
case ADF_AE_GROUP_3:
329+
return RP_GROUP_1;
330+
case ADF_AE_GROUP_2:
331+
if (get_fw_config(accel_dev) == adf_fw_cy_config)
332+
return RP_GROUP_0;
333+
else
334+
return RP_GROUP_1;
335+
default:
336+
dev_dbg(&GET_DEV(accel_dev), "ae_mask not recognized");
337+
return -EINVAL;
338+
}
339+
}
340+
341+
static u32 get_ena_thd_mask(struct adf_accel_dev *accel_dev, u32 obj_num)
342+
{
343+
const struct adf_fw_config *fw_config;
344+
345+
if (obj_num >= uof_get_num_objs(accel_dev))
346+
return ADF_GEN4_ENA_THD_MASK_ERROR;
347+
348+
fw_config = get_fw_config(accel_dev);
349+
if (!fw_config)
350+
return ADF_GEN4_ENA_THD_MASK_ERROR;
351+
352+
switch (fw_config[obj_num].obj) {
353+
case ADF_FW_ASYM_OBJ:
354+
return ENA_THD_MASK_ASYM;
355+
case ADF_FW_SYM_OBJ:
356+
return ENA_THD_MASK_SYM;
357+
case ADF_FW_DC_OBJ:
358+
return ENA_THD_MASK_DC;
359+
default:
360+
return ADF_GEN4_ENA_THD_MASK_ERROR;
361+
}
362+
}
392363

393364
static u16 get_ring_to_svc_map(struct adf_accel_dev *accel_dev)
394365
{
@@ -526,6 +497,8 @@ void adf_init_hw_data_420xx(struct adf_hw_device_data *hw_data, u32 dev_id)
526497
hw_data->uof_get_name = uof_get_name_420xx;
527498
hw_data->uof_get_num_objs = uof_get_num_objs;
528499
hw_data->uof_get_ae_mask = uof_get_ae_mask;
500+
hw_data->get_rp_group = get_rp_group;
501+
hw_data->get_ena_thd_mask = get_ena_thd_mask;
529502
hw_data->set_msix_rttable = adf_gen4_set_msix_default_rttable;
530503
hw_data->set_ssm_wdtimer = adf_gen4_set_ssm_wdtimer;
531504
hw_data->get_ring_to_svc_map = get_ring_to_svc_map;

‎drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c‎

Lines changed: 77 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,11 @@
2323
#define ADF_AE_GROUP_1 GENMASK(7, 4)
2424
#define ADF_AE_GROUP_2 BIT(8)
2525

26+
#define ENA_THD_MASK_ASYM GENMASK(1, 0)
27+
#define ENA_THD_MASK_ASYM_401XX GENMASK(5, 0)
28+
#define ENA_THD_MASK_SYM GENMASK(6, 0)
29+
#define ENA_THD_MASK_DC GENMASK(1, 0)
30+
2631
static const char * const adf_4xxx_fw_objs[] = {
2732
[ADF_FW_SYM_OBJ] = ADF_4XXX_SYM_OBJ,
2833
[ADF_FW_ASYM_OBJ] = ADF_4XXX_ASYM_OBJ,
@@ -86,25 +91,6 @@ static_assert(ARRAY_SIZE(adf_fw_cy_config) == ARRAY_SIZE(adf_fw_asym_dc_config))
8691
static_assert(ARRAY_SIZE(adf_fw_cy_config) == ARRAY_SIZE(adf_fw_sym_dc_config));
8792
static_assert(ARRAY_SIZE(adf_fw_cy_config) == ARRAY_SIZE(adf_fw_dcc_config));
8893

89-
/* Worker thread to service arbiter mappings */
90-
static const u32 default_thrd_to_arb_map[ADF_4XXX_MAX_ACCELENGINES] = {
91-
0x5555555, 0x5555555, 0x5555555, 0x5555555,
92-
0xAAAAAAA, 0xAAAAAAA, 0xAAAAAAA, 0xAAAAAAA,
93-
0x0
94-
};
95-
96-
static const u32 thrd_to_arb_map_dc[ADF_4XXX_MAX_ACCELENGINES] = {
97-
0x000000FF, 0x000000FF, 0x000000FF, 0x000000FF,
98-
0x000000FF, 0x000000FF, 0x000000FF, 0x000000FF,
99-
0x0
100-
};
101-
102-
static const u32 thrd_to_arb_map_dcc[ADF_4XXX_MAX_ACCELENGINES] = {
103-
0x00000000, 0x00000000, 0x00000000, 0x00000000,
104-
0x0000FFFF, 0x0000FFFF, 0x0000FFFF, 0x0000FFFF,
105-
0x0
106-
};
107-
10894
static struct adf_hw_device_class adf_4xxx_class = {
10995
.name = ADF_4XXX_DEVICE_NAME,
11096
.type = DEV_4XXX,
@@ -220,14 +206,11 @@ static u32 get_accel_cap(struct adf_accel_dev *accel_dev)
220206

221207
static const u32 *adf_get_arbiter_mapping(struct adf_accel_dev *accel_dev)
222208
{
223-
switch (adf_get_service_enabled(accel_dev)) {
224-
case SVC_DC:
225-
return thrd_to_arb_map_dc;
226-
case SVC_DCC:
227-
return thrd_to_arb_map_dcc;
228-
default:
229-
return default_thrd_to_arb_map;
230-
}
209+
if (adf_gen4_init_thd2arb_map(accel_dev))
210+
dev_warn(&GET_DEV(accel_dev),
211+
"Generate of the thread to arbiter map failed");
212+
213+
return GET_HW_DATA(accel_dev)->thd_to_arb_map;
231214
}
232215

233216
static void adf_init_rl_data(struct adf_rl_hw_data *rl_data)
@@ -278,11 +261,64 @@ static const struct adf_fw_config *get_fw_config(struct adf_accel_dev *accel_dev
278261
}
279262
}
280263

281-
enum adf_rp_groups {
282-
RP_GROUP_0 = 0,
283-
RP_GROUP_1,
284-
RP_GROUP_COUNT
285-
};
264+
static int get_rp_group(struct adf_accel_dev *accel_dev, u32 ae_mask)
265+
{
266+
switch (ae_mask) {
267+
case ADF_AE_GROUP_0:
268+
return RP_GROUP_0;
269+
case ADF_AE_GROUP_1:
270+
return RP_GROUP_1;
271+
default:
272+
dev_dbg(&GET_DEV(accel_dev), "ae_mask not recognized");
273+
return -EINVAL;
274+
}
275+
}
276+
277+
static u32 get_ena_thd_mask(struct adf_accel_dev *accel_dev, u32 obj_num)
278+
{
279+
const struct adf_fw_config *fw_config;
280+
281+
if (obj_num >= uof_get_num_objs(accel_dev))
282+
return ADF_GEN4_ENA_THD_MASK_ERROR;
283+
284+
fw_config = get_fw_config(accel_dev);
285+
if (!fw_config)
286+
return ADF_GEN4_ENA_THD_MASK_ERROR;
287+
288+
switch (fw_config[obj_num].obj) {
289+
case ADF_FW_ASYM_OBJ:
290+
return ENA_THD_MASK_ASYM;
291+
case ADF_FW_SYM_OBJ:
292+
return ENA_THD_MASK_SYM;
293+
case ADF_FW_DC_OBJ:
294+
return ENA_THD_MASK_DC;
295+
default:
296+
return ADF_GEN4_ENA_THD_MASK_ERROR;
297+
}
298+
}
299+
300+
static u32 get_ena_thd_mask_401xx(struct adf_accel_dev *accel_dev, u32 obj_num)
301+
{
302+
const struct adf_fw_config *fw_config;
303+
304+
if (obj_num >= uof_get_num_objs(accel_dev))
305+
return ADF_GEN4_ENA_THD_MASK_ERROR;
306+
307+
fw_config = get_fw_config(accel_dev);
308+
if (!fw_config)
309+
return ADF_GEN4_ENA_THD_MASK_ERROR;
310+
311+
switch (fw_config[obj_num].obj) {
312+
case ADF_FW_ASYM_OBJ:
313+
return ENA_THD_MASK_ASYM_401XX;
314+
case ADF_FW_SYM_OBJ:
315+
return ENA_THD_MASK_SYM;
316+
case ADF_FW_DC_OBJ:
317+
return ENA_THD_MASK_DC;
318+
default:
319+
return ADF_GEN4_ENA_THD_MASK_ERROR;
320+
}
321+
}
286322

287323
static u16 get_ring_to_svc_map(struct adf_accel_dev *accel_dev)
288324
{
@@ -428,14 +464,22 @@ void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data, u32 dev_id)
428464
hw_data->fw_mmp_name = ADF_402XX_MMP;
429465
hw_data->uof_get_name = uof_get_name_402xx;
430466
break;
431-
467+
case ADF_401XX_PCI_DEVICE_ID:
468+
hw_data->fw_name = ADF_4XXX_FW;
469+
hw_data->fw_mmp_name = ADF_4XXX_MMP;
470+
hw_data->uof_get_name = uof_get_name_4xxx;
471+
hw_data->get_ena_thd_mask = get_ena_thd_mask_401xx;
472+
break;
432473
default:
433474
hw_data->fw_name = ADF_4XXX_FW;
434475
hw_data->fw_mmp_name = ADF_4XXX_MMP;
435476
hw_data->uof_get_name = uof_get_name_4xxx;
477+
hw_data->get_ena_thd_mask = get_ena_thd_mask;
478+
break;
436479
}
437480
hw_data->uof_get_num_objs = uof_get_num_objs;
438481
hw_data->uof_get_ae_mask = uof_get_ae_mask;
482+
hw_data->get_rp_group = get_rp_group;
439483
hw_data->set_msix_rttable = adf_gen4_set_msix_default_rttable;
440484
hw_data->set_ssm_wdtimer = adf_gen4_set_ssm_wdtimer;
441485
hw_data->get_ring_to_svc_map = get_ring_to_svc_map;

‎drivers/crypto/intel/qat/qat_common/adf_accel_devices.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@
1313
#include "adf_rl.h"
1414
#include "adf_telemetry.h"
1515
#include "adf_pfvf_msg.h"
16+
#include "icp_qat_hw.h"
1617

1718
#define ADF_DH895XCC_DEVICE_NAME "dh895xcc"
1819
#define ADF_DH895XCCVF_DEVICE_NAME "dh895xccvf"
@@ -248,6 +249,8 @@ struct adf_hw_device_data {
248249
const char *(*uof_get_name)(struct adf_accel_dev *accel_dev, u32 obj_num);
249250
u32 (*uof_get_num_objs)(struct adf_accel_dev *accel_dev);
250251
u32 (*uof_get_ae_mask)(struct adf_accel_dev *accel_dev, u32 obj_num);
252+
int (*get_rp_group)(struct adf_accel_dev *accel_dev, u32 ae_mask);
253+
u32 (*get_ena_thd_mask)(struct adf_accel_dev *accel_dev, u32 obj_num);
251254
int (*dev_config)(struct adf_accel_dev *accel_dev);
252255
struct adf_pfvf_ops pfvf_ops;
253256
struct adf_hw_csr_ops csr_ops;
@@ -270,6 +273,7 @@ struct adf_hw_device_data {
270273
u32 admin_ae_mask;
271274
u16 tx_rings_mask;
272275
u16 ring_to_svc_map;
276+
u32 thd_to_arb_map[ICP_QAT_HW_AE_DELIMITER];
273277
u8 tx_rx_gap;
274278
u8 num_banks;
275279
u16 num_banks_per_vf;

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