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| 1 | +Texas Instruments K3 Interrupt Router |
| 2 | +===================================== |
| 3 | + |
| 4 | +The Interrupt Router (INTR) module provides a mechanism to mux M |
| 5 | +interrupt inputs to N interrupt outputs, where all M inputs are selectable |
| 6 | +to be driven per N output. An Interrupt Router can either handle edge triggered |
| 7 | +or level triggered interrupts and that is fixed in hardware. |
| 8 | + |
| 9 | + Interrupt Router |
| 10 | + +----------------------+ |
| 11 | + | Inputs Outputs | |
| 12 | + +-------+ | +------+ +-----+ | |
| 13 | + | GPIO |----------->| | irq0 | | 0 | | Host IRQ |
| 14 | + +-------+ | +------+ +-----+ | controller |
| 15 | + | . . | +-------+ |
| 16 | + +-------+ | . . |----->| IRQ | |
| 17 | + | INTA |----------->| . . | +-------+ |
| 18 | + +-------+ | . +-----+ | |
| 19 | + | +------+ | N | | |
| 20 | + | | irqM | +-----+ | |
| 21 | + | +------+ | |
| 22 | + | | |
| 23 | + +----------------------+ |
| 24 | + |
| 25 | +There is one register per output (MUXCNTL_N) that controls the selection. |
| 26 | +Configuration of these MUXCNTL_N registers is done by a system controller |
| 27 | +(like the Device Memory and Security Controller on K3 AM654 SoC). System |
| 28 | +controller will keep track of the used and unused registers within the Router. |
| 29 | +Driver should request the system controller to get the range of GIC IRQs |
| 30 | +assigned to the requesting hosts. It is the drivers responsibility to keep |
| 31 | +track of Host IRQs. |
| 32 | + |
| 33 | +Communication between the host processor running an OS and the system |
| 34 | +controller happens through a protocol called TI System Control Interface |
| 35 | +(TISCI protocol). For more details refer: |
| 36 | +Documentation/devicetree/bindings/arm/keystone/ti,sci.txt |
| 37 | + |
| 38 | +TISCI Interrupt Router Node: |
| 39 | +---------------------------- |
| 40 | +Required Properties: |
| 41 | +- compatible: Must be "ti,sci-intr". |
| 42 | +- ti,intr-trigger-type: Should be one of the following: |
| 43 | + 1: If intr supports edge triggered interrupts. |
| 44 | + 4: If intr supports level triggered interrupts. |
| 45 | +- interrupt-controller: Identifies the node as an interrupt controller |
| 46 | +- #interrupt-cells: Specifies the number of cells needed to encode an |
| 47 | + interrupt source. The value should be 2. |
| 48 | + First cell should contain the TISCI device ID of source |
| 49 | + Second cell should contain the interrupt source offset |
| 50 | + within the device. |
| 51 | +- ti,sci: Phandle to TI-SCI compatible System controller node. |
| 52 | +- ti,sci-dst-id: TISCI device ID of the destination IRQ controller. |
| 53 | +- ti,sci-rm-range-girq: Array of TISCI subtype ids representing the host irqs |
| 54 | + assigned to this interrupt router. Each subtype id |
| 55 | + corresponds to a range of host irqs. |
| 56 | + |
| 57 | +For more details on TISCI IRQ resource management refer: |
| 58 | +http://downloads.ti.com/tisci/esd/latest/2_tisci_msgs/rm/rm_irq.html |
| 59 | + |
| 60 | +Example: |
| 61 | +-------- |
| 62 | +The following example demonstrates both interrupt router node and the consumer |
| 63 | +node(main gpio) on the AM654 SoC: |
| 64 | + |
| 65 | +main_intr: interrupt-controller0 { |
| 66 | + compatible = "ti,sci-intr"; |
| 67 | + ti,intr-trigger-type = <1>; |
| 68 | + interrupt-controller; |
| 69 | + interrupt-parent = <&gic500>; |
| 70 | + #interrupt-cells = <2>; |
| 71 | + ti,sci = <&dmsc>; |
| 72 | + ti,sci-dst-id = <56>; |
| 73 | + ti,sci-rm-range-girq = <0x1>; |
| 74 | +}; |
| 75 | + |
| 76 | +main_gpio0: gpio@600000 { |
| 77 | + ... |
| 78 | + interrupt-parent = <&main_intr>; |
| 79 | + interrupts = <57 256>, <57 257>, <57 258>, |
| 80 | + <57 259>, <57 260>, <57 261>; |
| 81 | + ... |
| 82 | +}; |
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