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36 | 36 | #define OMAP4430_AUTO_CTRL_VDD_CORE(x) ((x) << 0) |
37 | 37 | #define OMAP4430_AUTO_CTRL_VDD_RET 2 |
38 | 38 |
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39 | | -#define OMAP4_VDD_DEFAULT_VAL \ |
| 39 | +#define OMAP4430_VDD_I2C_DISABLE_MASK \ |
40 | 40 | (OMAP4430_VDD_IVA_I2C_DISABLE | \ |
41 | | - OMAP4430_VDD_MPU_I2C_DISABLE | \ |
42 | | - OMAP4430_VDD_CORE_I2C_DISABLE | \ |
| 41 | + OMAP4430_VDD_MPU_I2C_DISABLE | \ |
| 42 | + OMAP4430_VDD_CORE_I2C_DISABLE) |
| 43 | + |
| 44 | +#define OMAP4_VDD_DEFAULT_VAL \ |
| 45 | + (OMAP4430_VDD_I2C_DISABLE_MASK | \ |
43 | 46 | OMAP4430_VDD_IVA_PRESENCE | OMAP4430_VDD_MPU_PRESENCE | \ |
44 | 47 | OMAP4430_AUTO_CTRL_VDD_IVA(OMAP4430_AUTO_CTRL_VDD_RET) | \ |
45 | 48 | OMAP4430_AUTO_CTRL_VDD_MPU(OMAP4430_AUTO_CTRL_VDD_RET) | \ |
46 | 49 | OMAP4430_AUTO_CTRL_VDD_CORE(OMAP4430_AUTO_CTRL_VDD_RET)) |
47 | 50 |
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| 51 | +#define OMAP4_VDD_RET_VAL \ |
| 52 | + (OMAP4_VDD_DEFAULT_VAL & ~OMAP4430_VDD_I2C_DISABLE_MASK) |
| 53 | + |
48 | 54 | /** |
49 | 55 | * struct omap_vc_channel_cfg - describe the cfg_channel bitfield |
50 | 56 | * @sa: bit for slave address |
@@ -299,6 +305,26 @@ void omap3_vc_set_pmic_signaling(int core_next_state) |
299 | 305 | } |
300 | 306 | } |
301 | 307 |
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| 308 | +void omap4_vc_set_pmic_signaling(int core_next_state) |
| 309 | +{ |
| 310 | + struct voltagedomain *vd = vc.vd; |
| 311 | + u32 val; |
| 312 | + |
| 313 | + if (!vd) |
| 314 | + return; |
| 315 | + |
| 316 | + switch (core_next_state) { |
| 317 | + case PWRDM_POWER_RET: |
| 318 | + val = OMAP4_VDD_RET_VAL; |
| 319 | + break; |
| 320 | + default: |
| 321 | + val = OMAP4_VDD_DEFAULT_VAL; |
| 322 | + break; |
| 323 | + } |
| 324 | + |
| 325 | + vd->write(val, OMAP4_PRM_VOLTCTRL_OFFSET); |
| 326 | +} |
| 327 | + |
302 | 328 | /* |
303 | 329 | * Configure signal polarity for sys_clkreq and sys_off_mode pins |
304 | 330 | * as the default values are wrong and can cause the system to hang |
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