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M-Vaittinenlag-linaro
M-Vaittinen
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lag-linaro
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mfd: bd71828, bd71815: Prepare for power-supply support
Add core support for ROHM BD718(15/28/78) PMIC's charger blocks. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Link: https://lore.kernel.org/r/20250821-bd71828-charger-v3-1-cc74ac4e0fb9@kemnade.info Signed-off-by: Lee Jones <lee@kernel.org>
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‎drivers/mfd/rohm-bd71828.c‎

Lines changed: 35 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -45,8 +45,8 @@ static const struct resource bd71828_rtc_irqs[] = {
4545

4646
static const struct resource bd71815_power_irqs[] = {
4747
DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_RMV, "bd71815-dcin-rmv"),
48-
DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_OUT, "bd71815-clps-out"),
49-
DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_IN, "bd71815-clps-in"),
48+
DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_OUT, "bd71815-dcin-clps-out"),
49+
DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_IN, "bd71815-dcin-clps-in"),
5050
DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_OVP_RES, "bd71815-dcin-ovp-res"),
5151
DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_OVP_DET, "bd71815-dcin-ovp-det"),
5252
DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_MON_RES, "bd71815-dcin-mon-res"),
@@ -56,7 +56,7 @@ static const struct resource bd71815_power_irqs[] = {
5656
DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_LOW_RES, "bd71815-vsys-low-res"),
5757
DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_LOW_DET, "bd71815-vsys-low-det"),
5858
DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_MON_RES, "bd71815-vsys-mon-res"),
59-
DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_MON_RES, "bd71815-vsys-mon-det"),
59+
DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_MON_DET, "bd71815-vsys-mon-det"),
6060
DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_WDG_TEMP, "bd71815-chg-wdg-temp"),
6161
DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_WDG_TIME, "bd71815-chg-wdg"),
6262
DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RECHARGE_RES, "bd71815-rechg-res"),
@@ -87,10 +87,10 @@ static const struct resource bd71815_power_irqs[] = {
8787
DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_2_DET, "bd71815-bat-oc2-det"),
8888
DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_3_RES, "bd71815-bat-oc3-res"),
8989
DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_3_DET, "bd71815-bat-oc3-det"),
90-
DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_RES, "bd71815-bat-low-res"),
91-
DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_DET, "bd71815-bat-low-det"),
92-
DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_RES, "bd71815-bat-hi-res"),
93-
DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_DET, "bd71815-bat-hi-det"),
90+
DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_RES, "bd71815-temp-bat-low-res"),
91+
DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_DET, "bd71815-temp-bat-low-det"),
92+
DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_RES, "bd71815-temp-bat-hi-res"),
93+
DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_DET, "bd71815-temp-bat-hi-det"),
9494
};
9595

9696
static const struct mfd_cell bd71815_mfd_cells[] = {
@@ -109,7 +109,30 @@ static const struct mfd_cell bd71815_mfd_cells[] = {
109109
},
110110
};
111111

112-
static const struct mfd_cell bd71828_mfd_cells[] = {
112+
static const struct resource bd71828_power_irqs[] = {
113+
DEFINE_RES_IRQ_NAMED(BD71828_INT_CHG_TOPOFF_TO_DONE,
114+
"bd71828-chg-done"),
115+
DEFINE_RES_IRQ_NAMED(BD71828_INT_DCIN_DET, "bd71828-pwr-dcin-in"),
116+
DEFINE_RES_IRQ_NAMED(BD71828_INT_DCIN_RMV, "bd71828-pwr-dcin-out"),
117+
DEFINE_RES_IRQ_NAMED(BD71828_INT_BAT_LOW_VOLT_RES,
118+
"bd71828-vbat-normal"),
119+
DEFINE_RES_IRQ_NAMED(BD71828_INT_BAT_LOW_VOLT_DET, "bd71828-vbat-low"),
120+
DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_HI_DET, "bd71828-btemp-hi"),
121+
DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_HI_RES, "bd71828-btemp-cool"),
122+
DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_LOW_DET, "bd71828-btemp-lo"),
123+
DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_LOW_RES,
124+
"bd71828-btemp-warm"),
125+
DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_VF_DET,
126+
"bd71828-temp-hi"),
127+
DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_VF_RES,
128+
"bd71828-temp-norm"),
129+
DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_125_DET,
130+
"bd71828-temp-125-over"),
131+
DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_125_RES,
132+
"bd71828-temp-125-under"),
133+
};
134+
135+
static struct mfd_cell bd71828_mfd_cells[] = {
113136
{ .name = "bd71828-pmic", },
114137
{ .name = "bd71828-gpio", },
115138
{ .name = "bd71828-led", .of_compatible = "rohm,bd71828-leds" },
@@ -118,8 +141,11 @@ static const struct mfd_cell bd71828_mfd_cells[] = {
118141
* BD70528 clock gate are the register address and mask.
119142
*/
120143
{ .name = "bd71828-clk", },
121-
{ .name = "bd71827-power", },
122144
{
145+
.name = "bd71828-power",
146+
.resources = bd71828_power_irqs,
147+
.num_resources = ARRAY_SIZE(bd71828_power_irqs),
148+
}, {
123149
.name = "bd71828-rtc",
124150
.resources = bd71828_rtc_irqs,
125151
.num_resources = ARRAY_SIZE(bd71828_rtc_irqs),

‎include/linux/mfd/rohm-bd71828.h‎

Lines changed: 63 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -189,6 +189,69 @@ enum {
189189
/* Charger/Battey */
190190
#define BD71828_REG_CHG_STATE 0x65
191191
#define BD71828_REG_CHG_FULL 0xd2
192+
#define BD71828_REG_CHG_EN 0x6F
193+
#define BD71828_REG_DCIN_STAT 0x68
194+
#define BD71828_MASK_DCIN_DET 0x01
195+
#define BD71828_REG_VDCIN_U 0x9c
196+
#define BD71828_MASK_CHG_EN 0x01
197+
#define BD71828_CHG_MASK_DCIN_U 0x0f
198+
#define BD71828_REG_BAT_STAT 0x67
199+
#define BD71828_REG_BAT_TEMP 0x6c
200+
#define BD71828_MASK_BAT_TEMP 0x07
201+
#define BD71828_BAT_TEMP_OPEN 0x07
202+
#define BD71828_MASK_BAT_DET 0x20
203+
#define BD71828_MASK_BAT_DET_DONE 0x10
204+
#define BD71828_REG_CHG_STATE 0x65
205+
#define BD71828_REG_VBAT_U 0x8c
206+
#define BD71828_MASK_VBAT_U 0x0f
207+
#define BD71828_REG_VBAT_REX_AVG_U 0x92
208+
209+
#define BD71828_REG_OCV_PWRON_U 0x8A
210+
211+
#define BD71828_REG_VBAT_MIN_AVG_U 0x8e
212+
#define BD71828_REG_VBAT_MIN_AVG_L 0x8f
213+
214+
#define BD71828_REG_CC_CNT3 0xb5
215+
#define BD71828_REG_CC_CNT2 0xb6
216+
#define BD71828_REG_CC_CNT1 0xb7
217+
#define BD71828_REG_CC_CNT0 0xb8
218+
#define BD71828_REG_CC_CURCD_AVG_U 0xb2
219+
#define BD71828_MASK_CC_CURCD_AVG_U 0x3f
220+
#define BD71828_MASK_CC_CUR_DIR 0x80
221+
#define BD71828_REG_VM_BTMP_U 0xa1
222+
#define BD71828_REG_VM_BTMP_L 0xa2
223+
#define BD71828_MASK_VM_BTMP_U 0x0f
224+
#define BD71828_REG_COULOMB_CTRL 0xc4
225+
#define BD71828_REG_COULOMB_CTRL2 0xd2
226+
#define BD71828_MASK_REX_CC_CLR 0x01
227+
#define BD71828_MASK_FULL_CC_CLR 0x10
228+
#define BD71828_REG_CC_CNT_FULL3 0xbd
229+
#define BD71828_REG_CC_CNT_CHG3 0xc1
230+
231+
#define BD71828_REG_VBAT_INITIAL1_U 0x86
232+
#define BD71828_REG_VBAT_INITIAL1_L 0x87
233+
234+
#define BD71828_REG_VBAT_INITIAL2_U 0x88
235+
#define BD71828_REG_VBAT_INITIAL2_L 0x89
236+
237+
#define BD71828_REG_IBAT_U 0xb0
238+
#define BD71828_REG_IBAT_L 0xb1
239+
240+
#define BD71828_REG_IBAT_AVG_U 0xb2
241+
#define BD71828_REG_IBAT_AVG_L 0xb3
242+
243+
#define BD71828_REG_VSYS_AVG_U 0x96
244+
#define BD71828_REG_VSYS_AVG_L 0x97
245+
#define BD71828_REG_VSYS_MIN_AVG_U 0x98
246+
#define BD71828_REG_VSYS_MIN_AVG_L 0x99
247+
#define BD71828_REG_CHG_SET1 0x75
248+
#define BD71828_REG_ALM_VBAT_LIMIT_U 0xaa
249+
#define BD71828_REG_BATCAP_MON_LIMIT_U 0xcc
250+
#define BD71828_REG_CONF 0x64
251+
252+
#define BD71828_REG_DCIN_CLPS 0x71
253+
254+
#define BD71828_REG_MEAS_CLEAR 0xaf
192255

193256
/* LEDs */
194257
#define BD71828_REG_LED_CTRL 0x4A

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