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clk: qcom: gcc: Add support for Global Clock controller found on MSM8226
Modify existing MSM8974 driver to support MSM8226 SoC. Override frequencies which are different in this older chip. Register all the clocks to the framework for the clients to be able to request for them. Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl> Link: https://lore.kernel.org/r/20210418122909.71434-3-bartosz.dudziak@snejp.pl Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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‎drivers/clk/qcom/gcc-msm8974.c‎

Lines changed: 162 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -719,6 +719,12 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
719719
},
720720
};
721721

722+
static const struct freq_tbl ftbl_gcc_ce1_clk_msm8226[] = {
723+
F(50000000, P_GPLL0, 12, 0, 0),
724+
F(100000000, P_GPLL0, 6, 0, 0),
725+
{ }
726+
};
727+
722728
static const struct freq_tbl ftbl_gcc_ce1_clk[] = {
723729
F(50000000, P_GPLL0, 12, 0, 0),
724730
F(75000000, P_GPLL0, 8, 0, 0),
@@ -761,6 +767,11 @@ static struct clk_rcg2 ce2_clk_src = {
761767
},
762768
};
763769

770+
static const struct freq_tbl ftbl_gcc_gp_clk_msm8226[] = {
771+
F(19200000, P_XO, 1, 0, 0),
772+
{ }
773+
};
774+
764775
static const struct freq_tbl ftbl_gcc_gp_clk[] = {
765776
F(4800000, P_XO, 4, 0, 0),
766777
F(6000000, P_GPLL0, 10, 1, 10),
@@ -1955,6 +1966,10 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
19551966
.enable_mask = BIT(0),
19561967
.hw.init = &(struct clk_init_data){
19571968
.name = "gcc_mss_q6_bimc_axi_clk",
1969+
.parent_names = (const char *[]){
1970+
"system_noc_clk_src",
1971+
},
1972+
.num_parents = 1,
19581973
.ops = &clk_branch2_ops,
19591974
},
19601975
},
@@ -1993,6 +2008,20 @@ static struct clk_branch gcc_pdm_ahb_clk = {
19932008
},
19942009
};
19952010

2011+
static struct clk_branch gcc_pdm_xo4_clk = {
2012+
.halt_reg = 0x0cc8,
2013+
.clkr = {
2014+
.enable_reg = 0x0cc8,
2015+
.enable_mask = BIT(0),
2016+
.hw.init = &(struct clk_init_data){
2017+
.name = "gcc_pdm_xo4_clk",
2018+
.parent_names = (const char *[]){ "xo" },
2019+
.num_parents = 1,
2020+
.ops = &clk_branch2_ops,
2021+
},
2022+
},
2023+
};
2024+
19962025
static struct clk_branch gcc_prng_ahb_clk = {
19972026
.halt_reg = 0x0d04,
19982027
.halt_check = BRANCH_HALT_VOTED,
@@ -2430,6 +2459,121 @@ static struct gdsc usb_hs_hsic_gdsc = {
24302459
.pwrsts = PWRSTS_OFF_ON,
24312460
};
24322461

2462+
static struct clk_regmap *gcc_msm8226_clocks[] = {
2463+
[GPLL0] = &gpll0.clkr,
2464+
[GPLL0_VOTE] = &gpll0_vote,
2465+
[GPLL1] = &gpll1.clkr,
2466+
[GPLL1_VOTE] = &gpll1_vote,
2467+
[CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
2468+
[PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
2469+
[SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
2470+
[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2471+
[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2472+
[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2473+
[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2474+
[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2475+
[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2476+
[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2477+
[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2478+
[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2479+
[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2480+
[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2481+
[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2482+
[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2483+
[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2484+
[BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2485+
[BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
2486+
[BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
2487+
[BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
2488+
[CE1_CLK_SRC] = &ce1_clk_src.clkr,
2489+
[GP1_CLK_SRC] = &gp1_clk_src.clkr,
2490+
[GP2_CLK_SRC] = &gp2_clk_src.clkr,
2491+
[GP3_CLK_SRC] = &gp3_clk_src.clkr,
2492+
[PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2493+
[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2494+
[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2495+
[SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
2496+
[USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2497+
[USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr,
2498+
[USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr,
2499+
[USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr,
2500+
[GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr,
2501+
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2502+
[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2503+
[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2504+
[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2505+
[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2506+
[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2507+
[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2508+
[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2509+
[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2510+
[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2511+
[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2512+
[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2513+
[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2514+
[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2515+
[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2516+
[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2517+
[GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
2518+
[GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
2519+
[GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
2520+
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2521+
[GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
2522+
[GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
2523+
[GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
2524+
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2525+
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2526+
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2527+
[GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
2528+
[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
2529+
[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
2530+
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2531+
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2532+
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
2533+
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2534+
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2535+
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2536+
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2537+
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2538+
[GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
2539+
[GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
2540+
[GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
2541+
[GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
2542+
[GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2543+
[GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr,
2544+
[GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr,
2545+
[GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr,
2546+
[GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr,
2547+
};
2548+
2549+
static const struct qcom_reset_map gcc_msm8226_resets[] = {
2550+
[GCC_USB_HS_HSIC_BCR] = { 0x0400 },
2551+
[GCC_USB_HS_BCR] = { 0x0480 },
2552+
[GCC_USB2A_PHY_BCR] = { 0x04a8 },
2553+
};
2554+
2555+
static struct gdsc *gcc_msm8226_gdscs[] = {
2556+
[USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc,
2557+
};
2558+
2559+
static const struct regmap_config gcc_msm8226_regmap_config = {
2560+
.reg_bits = 32,
2561+
.reg_stride = 4,
2562+
.val_bits = 32,
2563+
.max_register = 0x1a80,
2564+
.fast_io = true,
2565+
};
2566+
2567+
static const struct qcom_cc_desc gcc_msm8226_desc = {
2568+
.config = &gcc_msm8226_regmap_config,
2569+
.clks = gcc_msm8226_clocks,
2570+
.num_clks = ARRAY_SIZE(gcc_msm8226_clocks),
2571+
.resets = gcc_msm8226_resets,
2572+
.num_resets = ARRAY_SIZE(gcc_msm8226_resets),
2573+
.gdscs = gcc_msm8226_gdscs,
2574+
.num_gdscs = ARRAY_SIZE(gcc_msm8226_gdscs),
2575+
};
2576+
24332577
static struct clk_regmap *gcc_msm8974_clocks[] = {
24342578
[GPLL0] = &gpll0.clkr,
24352579
[GPLL0_VOTE] = &gpll0_vote,
@@ -2682,13 +2826,22 @@ static const struct qcom_cc_desc gcc_msm8974_desc = {
26822826
};
26832827

26842828
static const struct of_device_id gcc_msm8974_match_table[] = {
2685-
{ .compatible = "qcom,gcc-msm8974" },
2686-
{ .compatible = "qcom,gcc-msm8974pro" , .data = (void *)1UL },
2687-
{ .compatible = "qcom,gcc-msm8974pro-ac", .data = (void *)1UL },
2829+
{ .compatible = "qcom,gcc-msm8226", .data = &gcc_msm8226_desc },
2830+
{ .compatible = "qcom,gcc-msm8974", .data = &gcc_msm8974_desc },
2831+
{ .compatible = "qcom,gcc-msm8974pro", .data = &gcc_msm8974_desc },
2832+
{ .compatible = "qcom,gcc-msm8974pro-ac", .data = &gcc_msm8974_desc },
26882833
{ }
26892834
};
26902835
MODULE_DEVICE_TABLE(of, gcc_msm8974_match_table);
26912836

2837+
static void msm8226_clock_override(void)
2838+
{
2839+
ce1_clk_src.freq_tbl = ftbl_gcc_ce1_clk_msm8226;
2840+
gp1_clk_src.freq_tbl = ftbl_gcc_gp_clk_msm8226;
2841+
gp2_clk_src.freq_tbl = ftbl_gcc_gp_clk_msm8226;
2842+
gp3_clk_src.freq_tbl = ftbl_gcc_gp_clk_msm8226;
2843+
}
2844+
26922845
static void msm8974_pro_clock_override(void)
26932846
{
26942847
sdcc1_apps_clk_src_init.parent_names = gcc_xo_gpll0_gpll4;
@@ -2708,16 +2861,18 @@ static int gcc_msm8974_probe(struct platform_device *pdev)
27082861
{
27092862
int ret;
27102863
struct device *dev = &pdev->dev;
2711-
bool pro;
27122864
const struct of_device_id *id;
27132865

27142866
id = of_match_device(gcc_msm8974_match_table, dev);
27152867
if (!id)
27162868
return -ENODEV;
2717-
pro = !!(id->data);
27182869

2719-
if (pro)
2720-
msm8974_pro_clock_override();
2870+
if (!of_device_is_compatible(dev->of_node, "qcom,gcc-msm8974")) {
2871+
if (id->data == &gcc_msm8226_desc)
2872+
msm8226_clock_override();
2873+
else
2874+
msm8974_pro_clock_override();
2875+
}
27212876

27222877
ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000);
27232878
if (ret)

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