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captain5050weilinwacalebbiggers
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namhyung
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perf vendor events: Add westmereex counter information
Add counter information necessary for optimizing event grouping the perf tool. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ The information was added in: intel/perfmon@475892a and later patches. Co-authored-by: Weilin Wang <weilin.wang@intel.com> Co-authored-by: Caleb Biggers <caleb.biggers@intel.com> Signed-off-by: Ian Rogers <irogers@google.com> Reviewed-by: Kan Liang <kan.liang@linux.intel.com> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: Namhyung Kim <namhyung@kernel.org> Link: https://lore.kernel.org/r/20240620181752.3945845-38-irogers@google.com
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‎tools/perf/pmu-events/arch/x86/westmereex/cache.json‎

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‎tools/perf/pmu-events/arch/x86/westmereex/counter.json‎

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[
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{
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"Unit": "core",
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"CountersNumFixed": "4",
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"CountersNumGeneric": "4"
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}
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]

‎tools/perf/pmu-events/arch/x86/westmereex/floating-point.json‎

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[
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{
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"BriefDescription": "X87 Floating point assists (Precise Event)",
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"Counter": "0,1,2,3",
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"EventCode": "0xF7",
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"EventName": "FP_ASSIST.ALL",
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"PEBS": "1",
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},
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{
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"BriefDescription": "X87 Floating point assists for invalid input value (Precise Event)",
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"Counter": "0,1,2,3",
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"EventCode": "0xF7",
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"EventName": "FP_ASSIST.INPUT",
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"PEBS": "1",
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},
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{
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"BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)",
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"Counter": "0,1,2,3",
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"EventCode": "0xF7",
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"EventName": "FP_ASSIST.OUTPUT",
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"PEBS": "1",
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},
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{
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"BriefDescription": "MMX Uops",
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"Counter": "0,1,2,3",
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"EventCode": "0x10",
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"EventName": "FP_COMP_OPS_EXE.MMX",
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"SampleAfterValue": "2000000",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "SSE2 integer Uops",
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"Counter": "0,1,2,3",
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"EventCode": "0x10",
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"EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER",
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"SampleAfterValue": "2000000",
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"UMask": "0x8"
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},
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{
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"BriefDescription": "SSE* FP double precision Uops",
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"Counter": "0,1,2,3",
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"EventCode": "0x10",
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"EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",
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"SampleAfterValue": "2000000",
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"UMask": "0x80"
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},
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{
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"BriefDescription": "SSE and SSE2 FP Uops",
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"Counter": "0,1,2,3",
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"EventCode": "0x10",
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"EventName": "FP_COMP_OPS_EXE.SSE_FP",
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"SampleAfterValue": "2000000",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "SSE FP packed Uops",
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"Counter": "0,1,2,3",
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"EventCode": "0x10",
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"EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED",
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"SampleAfterValue": "2000000",
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"UMask": "0x10"
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},
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{
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"BriefDescription": "SSE FP scalar Uops",
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"Counter": "0,1,2,3",
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"EventCode": "0x10",
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"EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR",
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"SampleAfterValue": "2000000",
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"UMask": "0x20"
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},
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{
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"BriefDescription": "SSE* FP single precision Uops",
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"Counter": "0,1,2,3",
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"EventCode": "0x10",
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"EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",
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"SampleAfterValue": "2000000",
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"UMask": "0x40"
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},
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{
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"BriefDescription": "Computational floating-point operations executed",
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"Counter": "0,1,2,3",
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"EventCode": "0x10",
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"EventName": "FP_COMP_OPS_EXE.X87",
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"SampleAfterValue": "2000000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "All Floating Point to and from MMX transitions",
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"Counter": "0,1,2,3",
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"EventCode": "0xCC",
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"EventName": "FP_MMX_TRANS.ANY",
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"SampleAfterValue": "2000000",
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"UMask": "0x3"
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},
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{
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"BriefDescription": "Transitions from MMX to Floating Point instructions",
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"Counter": "0,1,2,3",
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"EventCode": "0xCC",
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"EventName": "FP_MMX_TRANS.TO_FP",
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"SampleAfterValue": "2000000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Transitions from Floating Point to MMX instructions",
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"Counter": "0,1,2,3",
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"EventCode": "0xCC",
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"EventName": "FP_MMX_TRANS.TO_MMX",
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"SampleAfterValue": "2000000",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "128 bit SIMD integer pack operations",
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"Counter": "0,1,2,3",
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"EventCode": "0x12",
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"EventName": "SIMD_INT_128.PACK",
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"SampleAfterValue": "200000",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "128 bit SIMD integer arithmetic operations",
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"Counter": "0,1,2,3",
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"EventCode": "0x12",
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"EventName": "SIMD_INT_128.PACKED_ARITH",
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"SampleAfterValue": "200000",
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"UMask": "0x20"
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},
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{
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"BriefDescription": "128 bit SIMD integer logical operations",
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"Counter": "0,1,2,3",
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"EventCode": "0x12",
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"EventName": "SIMD_INT_128.PACKED_LOGICAL",
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"SampleAfterValue": "200000",
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"UMask": "0x10"
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},
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{
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"BriefDescription": "128 bit SIMD integer multiply operations",
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"Counter": "0,1,2,3",
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"EventCode": "0x12",
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"EventName": "SIMD_INT_128.PACKED_MPY",
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"SampleAfterValue": "200000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "128 bit SIMD integer shift operations",
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"Counter": "0,1,2,3",
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"EventCode": "0x12",
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"EventName": "SIMD_INT_128.PACKED_SHIFT",
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"SampleAfterValue": "200000",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "128 bit SIMD integer shuffle/move operations",
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"Counter": "0,1,2,3",
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"EventCode": "0x12",
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"EventName": "SIMD_INT_128.SHUFFLE_MOVE",
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"SampleAfterValue": "200000",
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"UMask": "0x40"
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},
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{
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"BriefDescription": "128 bit SIMD integer unpack operations",
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"Counter": "0,1,2,3",
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"EventCode": "0x12",
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"EventName": "SIMD_INT_128.UNPACK",
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"SampleAfterValue": "200000",
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"UMask": "0x8"
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},
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{
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"BriefDescription": "SIMD integer 64 bit pack operations",
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"Counter": "0,1,2,3",
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"EventCode": "0xFD",
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"EventName": "SIMD_INT_64.PACK",
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"SampleAfterValue": "200000",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "SIMD integer 64 bit arithmetic operations",
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"Counter": "0,1,2,3",
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"EventCode": "0xFD",
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"EventName": "SIMD_INT_64.PACKED_ARITH",
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"SampleAfterValue": "200000",
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"UMask": "0x20"
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},
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{
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"BriefDescription": "SIMD integer 64 bit logical operations",
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"Counter": "0,1,2,3",
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"EventCode": "0xFD",
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"EventName": "SIMD_INT_64.PACKED_LOGICAL",
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"SampleAfterValue": "200000",
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"UMask": "0x10"
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},
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{
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"BriefDescription": "SIMD integer 64 bit packed multiply operations",
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"Counter": "0,1,2,3",
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"EventCode": "0xFD",
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"EventName": "SIMD_INT_64.PACKED_MPY",
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"SampleAfterValue": "200000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "SIMD integer 64 bit shift operations",
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"Counter": "0,1,2,3",
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"EventCode": "0xFD",
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"EventName": "SIMD_INT_64.PACKED_SHIFT",
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"SampleAfterValue": "200000",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "SIMD integer 64 bit shuffle/move operations",
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"Counter": "0,1,2,3",
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"EventCode": "0xFD",
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"EventName": "SIMD_INT_64.SHUFFLE_MOVE",
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"SampleAfterValue": "200000",
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"UMask": "0x40"
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},
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{
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"BriefDescription": "SIMD integer 64 bit unpack operations",
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"Counter": "0,1,2,3",
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"EventCode": "0xFD",
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"EventName": "SIMD_INT_64.UNPACK",
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"SampleAfterValue": "200000",

‎tools/perf/pmu-events/arch/x86/westmereex/frontend.json‎

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[
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{
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"BriefDescription": "Instructions decoded",
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"Counter": "0,1,2,3",
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"EventCode": "0xD0",
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"EventName": "MACRO_INSTS.DECODED",
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"SampleAfterValue": "2000000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Macro-fused instructions decoded",
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"Counter": "0,1,2,3",
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"EventCode": "0xA6",
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"EventName": "MACRO_INSTS.FUSIONS_DECODED",
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"SampleAfterValue": "2000000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Two Uop instructions decoded",
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"Counter": "0,1,2,3",
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"EventCode": "0x19",
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"EventName": "TWO_UOP_INSTS_DECODED",
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"SampleAfterValue": "2000000",

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