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KAGA-KOKOKAGA-KOKO
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Merge branch 'x86/cpufeature' into x86/cache
Resolve the cpu/scattered conflict. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2 parents f410770 + 47bdf33 commit 7ce7f35

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‎CREDITS‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1864,10 +1864,11 @@ S: The Netherlands
18641864

18651865
N: Martin Kepplinger
18661866
E: martink@posteo.de
1867-
E: martin.kepplinger@theobroma-systems.com
1867+
E: martin.kepplinger@ginzinger.com
18681868
W: http://www.martinkepplinger.com
18691869
D: mma8452 accelerators iio driver
1870-
D: Kernel cleanups
1870+
D: pegasus_notetaker input driver
1871+
D: Kernel fixes and cleanups
18711872
S: Garnisonstraße 26
18721873
S: 4020 Linz
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S: Austria

‎Documentation/ABI/testing/sysfs-devices-system-ibm-rtl‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
What: state
1+
What: /sys/devices/system/ibm_rtl/state
22
Date: Sep 2010
33
KernelVersion: 2.6.37
44
Contact: Vernon Mauery <vernux@us.ibm.com>
@@ -10,7 +10,7 @@ Description: The state file allows a means by which to change in and
1010
Users: The ibm-prtm userspace daemon uses this interface.
1111

1212

13-
What: version
13+
What: /sys/devices/system/ibm_rtl/version
1414
Date: Sep 2010
1515
KernelVersion: 2.6.37
1616
Contact: Vernon Mauery <vernux@us.ibm.com>

‎Documentation/device-mapper/dm-raid.txt‎

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Original file line numberDiff line numberDiff line change
@@ -309,3 +309,4 @@ Version History
309309
with a reshape in progress.
310310
1.9.0 Add support for RAID level takeover/reshape/region size
311311
and set size reduction.
312+
1.9.1 Fix activation of existing RAID 4/10 mapped devices

‎Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,9 @@ Optional properties:
4343
reset signal present internally in some host controller IC designs.
4444
See Documentation/devicetree/bindings/reset/reset.txt for details.
4545

46+
* reset-names: request name for using "resets" property. Must be "reset".
47+
(It will be used together with "resets" property.)
48+
4649
* clocks: from common clock binding: handle to biu and ciu clocks for the
4750
bus interface unit clock and the card interface unit clock.
4851

@@ -103,6 +106,8 @@ board specific portions as listed below.
103106
interrupts = <0 75 0>;
104107
#address-cells = <1>;
105108
#size-cells = <0>;
109+
resets = <&rst 20>;
110+
reset-names = "reset";
106111
};
107112

108113
[board specific internal DMA resources]

‎Documentation/devicetree/bindings/net/marvell-orion-net.txt‎

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Original file line numberDiff line numberDiff line change
@@ -49,6 +49,7 @@ Optional port properties:
4949
and
5050

5151
- phy-handle: See ethernet.txt file in the same directory.
52+
- phy-mode: See ethernet.txt file in the same directory.
5253

5354
or
5455

‎Documentation/devicetree/bindings/pci/rockchip-pcie.txt‎

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -26,13 +26,16 @@ Required properties:
2626
- "sys"
2727
- "legacy"
2828
- "client"
29-
- resets: Must contain five entries for each entry in reset-names.
29+
- resets: Must contain seven entries for each entry in reset-names.
3030
See ../reset/reset.txt for details.
3131
- reset-names: Must include the following names
3232
- "core"
3333
- "mgmt"
3434
- "mgmt-sticky"
3535
- "pipe"
36+
- "pm"
37+
- "aclk"
38+
- "pclk"
3639
- pinctrl-names : The pin control state names
3740
- pinctrl-0: The "default" pinctrl state
3841
- #interrupt-cells: specifies the number of cells needed to encode an
@@ -86,8 +89,10 @@ pcie0: pcie@f8000000 {
8689
reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
8790
reg-names = "axi-base", "apb-base";
8891
resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
89-
<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
90-
reset-names = "core", "mgmt", "mgmt-sticky", "pipe";
92+
<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
93+
<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
94+
reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
95+
"pm", "pclk", "aclk";
9196
phys = <&pcie_phy>;
9297
phy-names = "pcie-phy";
9398
pinctrl-names = "default";

‎Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt‎

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Original file line numberDiff line numberDiff line change
@@ -14,11 +14,6 @@ Required properies:
1414
- #size-cells : The value of this property must be 1
1515
- ranges : defines mapping between pin controller node (parent) to
1616
gpio-bank node (children).
17-
- interrupt-parent: phandle of the interrupt parent to which the external
18-
GPIO interrupts are forwarded to.
19-
- st,syscfg: Should be phandle/offset pair. The phandle to the syscon node
20-
which includes IRQ mux selection register, and the offset of the IRQ mux
21-
selection register.
2217
- pins-are-numbered: Specify the subnodes are using numbered pinmux to
2318
specify pins.
2419

@@ -37,6 +32,11 @@ Required properties:
3732

3833
Optional properties:
3934
- reset: : Reference to the reset controller
35+
- interrupt-parent: phandle of the interrupt parent to which the external
36+
GPIO interrupts are forwarded to.
37+
- st,syscfg: Should be phandle/offset pair. The phandle to the syscon node
38+
which includes IRQ mux selection register, and the offset of the IRQ mux
39+
selection register.
4040

4141
Example:
4242
#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>

‎Documentation/devicetree/bindings/reset/uniphier-reset.txt‎

Lines changed: 31 additions & 31 deletions
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@@ -6,56 +6,56 @@ System reset
66

77
Required properties:
88
- compatible: should be one of the following:
9-
"socionext,uniphier-sld3-reset" - for PH1-sLD3 SoC.
10-
"socionext,uniphier-ld4-reset" - for PH1-LD4 SoC.
11-
"socionext,uniphier-pro4-reset" - for PH1-Pro4 SoC.
12-
"socionext,uniphier-sld8-reset" - for PH1-sLD8 SoC.
13-
"socionext,uniphier-pro5-reset" - for PH1-Pro5 SoC.
14-
"socionext,uniphier-pxs2-reset" - for ProXstream2/PH1-LD6b SoC.
15-
"socionext,uniphier-ld11-reset" - for PH1-LD11 SoC.
16-
"socionext,uniphier-ld20-reset" - for PH1-LD20 SoC.
9+
"socionext,uniphier-sld3-reset" - for sLD3 SoC.
10+
"socionext,uniphier-ld4-reset" - for LD4 SoC.
11+
"socionext,uniphier-pro4-reset" - for Pro4 SoC.
12+
"socionext,uniphier-sld8-reset" - for sLD8 SoC.
13+
"socionext,uniphier-pro5-reset" - for Pro5 SoC.
14+
"socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC.
15+
"socionext,uniphier-ld11-reset" - for LD11 SoC.
16+
"socionext,uniphier-ld20-reset" - for LD20 SoC.
1717
- #reset-cells: should be 1.
1818

1919
Example:
2020

2121
sysctrl@61840000 {
22-
compatible = "socionext,uniphier-ld20-sysctrl",
22+
compatible = "socionext,uniphier-ld11-sysctrl",
2323
"simple-mfd", "syscon";
2424
reg = <0x61840000 0x4000>;
2525

2626
reset {
27-
compatible = "socionext,uniphier-ld20-reset";
27+
compatible = "socionext,uniphier-ld11-reset";
2828
#reset-cells = <1>;
2929
};
3030

3131
other nodes ...
3232
};
3333

3434

35-
Media I/O (MIO) reset
36-
---------------------
35+
Media I/O (MIO) reset, SD reset
36+
-------------------------------
3737

3838
Required properties:
3939
- compatible: should be one of the following:
40-
"socionext,uniphier-sld3-mio-reset" - for PH1-sLD3 SoC.
41-
"socionext,uniphier-ld4-mio-reset" - for PH1-LD4 SoC.
42-
"socionext,uniphier-pro4-mio-reset" - for PH1-Pro4 SoC.
43-
"socionext,uniphier-sld8-mio-reset" - for PH1-sLD8 SoC.
44-
"socionext,uniphier-pro5-mio-reset" - for PH1-Pro5 SoC.
45-
"socionext,uniphier-pxs2-mio-reset" - for ProXstream2/PH1-LD6b SoC.
46-
"socionext,uniphier-ld11-mio-reset" - for PH1-LD11 SoC.
47-
"socionext,uniphier-ld20-mio-reset" - for PH1-LD20 SoC.
40+
"socionext,uniphier-sld3-mio-reset" - for sLD3 SoC.
41+
"socionext,uniphier-ld4-mio-reset" - for LD4 SoC.
42+
"socionext,uniphier-pro4-mio-reset" - for Pro4 SoC.
43+
"socionext,uniphier-sld8-mio-reset" - for sLD8 SoC.
44+
"socionext,uniphier-pro5-sd-reset" - for Pro5 SoC.
45+
"socionext,uniphier-pxs2-sd-reset" - for PXs2/LD6b SoC.
46+
"socionext,uniphier-ld11-mio-reset" - for LD11 SoC.
47+
"socionext,uniphier-ld20-sd-reset" - for LD20 SoC.
4848
- #reset-cells: should be 1.
4949

5050
Example:
5151

5252
mioctrl@59810000 {
53-
compatible = "socionext,uniphier-ld20-mioctrl",
53+
compatible = "socionext,uniphier-ld11-mioctrl",
5454
"simple-mfd", "syscon";
5555
reg = <0x59810000 0x800>;
5656

5757
reset {
58-
compatible = "socionext,uniphier-ld20-mio-reset";
58+
compatible = "socionext,uniphier-ld11-mio-reset";
5959
#reset-cells = <1>;
6060
};
6161

@@ -68,24 +68,24 @@ Peripheral reset
6868

6969
Required properties:
7070
- compatible: should be one of the following:
71-
"socionext,uniphier-ld4-peri-reset" - for PH1-LD4 SoC.
72-
"socionext,uniphier-pro4-peri-reset" - for PH1-Pro4 SoC.
73-
"socionext,uniphier-sld8-peri-reset" - for PH1-sLD8 SoC.
74-
"socionext,uniphier-pro5-peri-reset" - for PH1-Pro5 SoC.
75-
"socionext,uniphier-pxs2-peri-reset" - for ProXstream2/PH1-LD6b SoC.
76-
"socionext,uniphier-ld11-peri-reset" - for PH1-LD11 SoC.
77-
"socionext,uniphier-ld20-peri-reset" - for PH1-LD20 SoC.
71+
"socionext,uniphier-ld4-peri-reset" - for LD4 SoC.
72+
"socionext,uniphier-pro4-peri-reset" - for Pro4 SoC.
73+
"socionext,uniphier-sld8-peri-reset" - for sLD8 SoC.
74+
"socionext,uniphier-pro5-peri-reset" - for Pro5 SoC.
75+
"socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC.
76+
"socionext,uniphier-ld11-peri-reset" - for LD11 SoC.
77+
"socionext,uniphier-ld20-peri-reset" - for LD20 SoC.
7878
- #reset-cells: should be 1.
7979

8080
Example:
8181

8282
perictrl@59820000 {
83-
compatible = "socionext,uniphier-ld20-perictrl",
83+
compatible = "socionext,uniphier-ld11-perictrl",
8484
"simple-mfd", "syscon";
8585
reg = <0x59820000 0x200>;
8686

8787
reset {
88-
compatible = "socionext,uniphier-ld20-peri-reset";
88+
compatible = "socionext,uniphier-ld11-peri-reset";
8989
#reset-cells = <1>;
9090
};
9191

‎Documentation/devicetree/bindings/serial/cdns,uart.txt‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,9 @@
11
Binding for Cadence UART Controller
22

33
Required properties:
4-
- compatible : should be "cdns,uart-r1p8", or "xlnx,xuartps"
4+
- compatible :
5+
Use "xlnx,xuartps","cdns,uart-r1p8" for Zynq-7xxx SoC.
6+
Use "xlnx,zynqmp-uart","cdns,uart-r1p12" for Zynq Ultrascale+ MPSoC.
57
- reg: Should contain UART controller registers location and length.
68
- interrupts: Should contain UART controller interrupts.
79
- clocks: Must contain phandles to the UART clocks

‎Documentation/devicetree/bindings/serial/renesas,sci-serial.txt‎

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@@ -9,6 +9,14 @@ Required properties:
99
- "renesas,scifb-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFB compatible UART.
1010
- "renesas,scifa-r8a7740" for R8A7740 (R-Mobile A1) SCIFA compatible UART.
1111
- "renesas,scifb-r8a7740" for R8A7740 (R-Mobile A1) SCIFB compatible UART.
12+
- "renesas,scif-r8a7743" for R8A7743 (RZ/G1M) SCIF compatible UART.
13+
- "renesas,scifa-r8a7743" for R8A7743 (RZ/G1M) SCIFA compatible UART.
14+
- "renesas,scifb-r8a7743" for R8A7743 (RZ/G1M) SCIFB compatible UART.
15+
- "renesas,hscif-r8a7743" for R8A7743 (RZ/G1M) HSCIF compatible UART.
16+
- "renesas,scif-r8a7745" for R8A7745 (RZ/G1E) SCIF compatible UART.
17+
- "renesas,scifa-r8a7745" for R8A7745 (RZ/G1E) SCIFA compatible UART.
18+
- "renesas,scifb-r8a7745" for R8A7745 (RZ/G1E) SCIFB compatible UART.
19+
- "renesas,hscif-r8a7745" for R8A7745 (RZ/G1E) HSCIF compatible UART.
1220
- "renesas,scif-r8a7778" for R8A7778 (R-Car M1) SCIF compatible UART.
1321
- "renesas,scif-r8a7779" for R8A7779 (R-Car H1) SCIF compatible UART.
1422
- "renesas,scif-r8a7790" for R8A7790 (R-Car H2) SCIF compatible UART.

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