Skip to content

Commit 8908fdc

Browse files
nowrepalexdeucher
authored andcommitted
drm/amdgpu/vcn: Allow limiting ctx to instance 0 for AV1 at any time
There is no reason to require this to happen on first submitted IB only. We need to wait for the queue to be idle, but it can be done at any time (including when there are multiple video sessions active). Signed-off-by: David Rosca <david.rosca@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1 parent dc8f9f0 commit 8908fdc

File tree

2 files changed

+16
-8
lines changed

2 files changed

+16
-8
lines changed

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1886,15 +1886,19 @@ static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p,
18861886
struct amdgpu_job *job)
18871887
{
18881888
struct drm_gpu_scheduler **scheds;
1889-
1890-
/* The create msg must be in the first IB submitted */
1891-
if (atomic_read(&job->base.entity->fence_seq))
1892-
return -EINVAL;
1889+
struct dma_fence *fence;
18931890

18941891
/* if VCN0 is harvested, we can't support AV1 */
18951892
if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)
18961893
return -EINVAL;
18971894

1895+
/* wait for all jobs to finish before switching to instance 0 */
1896+
fence = amdgpu_ctx_get_fence(p->ctx, job->base.entity, ~0ull);
1897+
if (fence) {
1898+
dma_fence_wait(fence, false);
1899+
dma_fence_put(fence);
1900+
}
1901+
18981902
scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_DEC]
18991903
[AMDGPU_RING_PRIO_DEFAULT].sched;
19001904
drm_sched_entity_modify_sched(job->base.entity, scheds, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1804,15 +1804,19 @@ static int vcn_v4_0_limit_sched(struct amdgpu_cs_parser *p,
18041804
struct amdgpu_job *job)
18051805
{
18061806
struct drm_gpu_scheduler **scheds;
1807-
1808-
/* The create msg must be in the first IB submitted */
1809-
if (atomic_read(&job->base.entity->fence_seq))
1810-
return -EINVAL;
1807+
struct dma_fence *fence;
18111808

18121809
/* if VCN0 is harvested, we can't support AV1 */
18131810
if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)
18141811
return -EINVAL;
18151812

1813+
/* wait for all jobs to finish before switching to instance 0 */
1814+
fence = amdgpu_ctx_get_fence(p->ctx, job->base.entity, ~0ull);
1815+
if (fence) {
1816+
dma_fence_wait(fence, false);
1817+
dma_fence_put(fence);
1818+
}
1819+
18161820
scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_ENC]
18171821
[AMDGPU_RING_PRIO_0].sched;
18181822
drm_sched_entity_modify_sched(job->base.entity, scheds, 1);

0 commit comments

Comments
 (0)