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| 1 | +// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB |
| 2 | +/* Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */ |
| 3 | +#include <linux/mlx5/device.h> |
| 4 | +#include <net/psp.h> |
| 5 | +#include <linux/psp.h> |
| 6 | +#include "mlx5_core.h" |
| 7 | +#include "psp.h" |
| 8 | +#include "lib/crypto.h" |
| 9 | +#include "en_accel/psp.h" |
| 10 | + |
| 11 | +static int |
| 12 | +mlx5e_psp_set_config(struct psp_dev *psd, struct psp_dev_config *conf, |
| 13 | + struct netlink_ext_ack *extack) |
| 14 | +{ |
| 15 | + return 0; /* TODO: this should actually do things to the device */ |
| 16 | +} |
| 17 | + |
| 18 | +static int |
| 19 | +mlx5e_psp_generate_key_spi(struct mlx5_core_dev *mdev, |
| 20 | + enum mlx5_psp_gen_spi_in_key_size keysz, |
| 21 | + unsigned int keysz_bytes, |
| 22 | + struct psp_key_parsed *key) |
| 23 | +{ |
| 24 | + u32 out[MLX5_ST_SZ_DW(psp_gen_spi_out) + MLX5_ST_SZ_DW(key_spi)] = {}; |
| 25 | + u32 in[MLX5_ST_SZ_DW(psp_gen_spi_in)] = {}; |
| 26 | + void *outkey; |
| 27 | + int err; |
| 28 | + |
| 29 | + WARN_ON_ONCE(keysz_bytes > PSP_MAX_KEY); |
| 30 | + |
| 31 | + MLX5_SET(psp_gen_spi_in, in, opcode, MLX5_CMD_OP_PSP_GEN_SPI); |
| 32 | + MLX5_SET(psp_gen_spi_in, in, key_size, keysz); |
| 33 | + MLX5_SET(psp_gen_spi_in, in, num_of_spi, 1); |
| 34 | + err = mlx5_cmd_exec(mdev, in, sizeof(in), out, sizeof(out)); |
| 35 | + if (err) |
| 36 | + return err; |
| 37 | + |
| 38 | + outkey = MLX5_ADDR_OF(psp_gen_spi_out, out, key_spi); |
| 39 | + key->spi = cpu_to_be32(MLX5_GET(key_spi, outkey, spi)); |
| 40 | + memcpy(key->key, MLX5_ADDR_OF(key_spi, outkey, key) + 32 - keysz_bytes, |
| 41 | + keysz_bytes); |
| 42 | + |
| 43 | + return 0; |
| 44 | +} |
| 45 | + |
| 46 | +static int |
| 47 | +mlx5e_psp_rx_spi_alloc(struct psp_dev *psd, u32 version, |
| 48 | + struct psp_key_parsed *assoc, |
| 49 | + struct netlink_ext_ack *extack) |
| 50 | +{ |
| 51 | + struct mlx5e_priv *priv = netdev_priv(psd->main_netdev); |
| 52 | + enum mlx5_psp_gen_spi_in_key_size keysz; |
| 53 | + u8 keysz_bytes; |
| 54 | + |
| 55 | + switch (version) { |
| 56 | + case PSP_VERSION_HDR0_AES_GCM_128: |
| 57 | + keysz = MLX5_PSP_GEN_SPI_IN_KEY_SIZE_128; |
| 58 | + keysz_bytes = 16; |
| 59 | + break; |
| 60 | + case PSP_VERSION_HDR0_AES_GCM_256: |
| 61 | + keysz = MLX5_PSP_GEN_SPI_IN_KEY_SIZE_256; |
| 62 | + keysz_bytes = 32; |
| 63 | + break; |
| 64 | + default: |
| 65 | + return -EINVAL; |
| 66 | + } |
| 67 | + |
| 68 | + return mlx5e_psp_generate_key_spi(priv->mdev, keysz, keysz_bytes, assoc); |
| 69 | +} |
| 70 | + |
| 71 | +static int mlx5e_psp_assoc_add(struct psp_dev *psd, struct psp_assoc *pas, |
| 72 | + struct netlink_ext_ack *extack) |
| 73 | +{ |
| 74 | + struct mlx5e_priv *priv = netdev_priv(psd->main_netdev); |
| 75 | + |
| 76 | + mlx5_core_dbg(priv->mdev, "PSP assoc add: rx: %u, tx: %u\n", |
| 77 | + be32_to_cpu(pas->rx.spi), be32_to_cpu(pas->tx.spi)); |
| 78 | + |
| 79 | + return -EINVAL; |
| 80 | +} |
| 81 | + |
| 82 | +static void mlx5e_psp_assoc_del(struct psp_dev *psd, struct psp_assoc *pas) |
| 83 | +{ |
| 84 | +} |
| 85 | + |
| 86 | +static struct psp_dev_ops mlx5_psp_ops = { |
| 87 | + .set_config = mlx5e_psp_set_config, |
| 88 | + .rx_spi_alloc = mlx5e_psp_rx_spi_alloc, |
| 89 | + .tx_key_add = mlx5e_psp_assoc_add, |
| 90 | + .tx_key_del = mlx5e_psp_assoc_del, |
| 91 | +}; |
| 92 | + |
| 93 | +void mlx5e_psp_unregister(struct mlx5e_priv *priv) |
| 94 | +{ |
| 95 | + if (!priv->psp || !priv->psp->psp) |
| 96 | + return; |
| 97 | + |
| 98 | + psp_dev_unregister(priv->psp->psp); |
| 99 | +} |
| 100 | + |
| 101 | +void mlx5e_psp_register(struct mlx5e_priv *priv) |
| 102 | +{ |
| 103 | + /* FW Caps missing */ |
| 104 | + if (!priv->psp) |
| 105 | + return; |
| 106 | + |
| 107 | + priv->psp->caps.assoc_drv_spc = sizeof(u32); |
| 108 | + priv->psp->caps.versions = 1 << PSP_VERSION_HDR0_AES_GCM_128; |
| 109 | + if (MLX5_CAP_PSP(priv->mdev, psp_crypto_esp_aes_gcm_256_encrypt) && |
| 110 | + MLX5_CAP_PSP(priv->mdev, psp_crypto_esp_aes_gcm_256_decrypt)) |
| 111 | + priv->psp->caps.versions |= 1 << PSP_VERSION_HDR0_AES_GCM_256; |
| 112 | + |
| 113 | + priv->psp->psp = psp_dev_create(priv->netdev, &mlx5_psp_ops, |
| 114 | + &priv->psp->caps, NULL); |
| 115 | + if (IS_ERR(priv->psp->psp)) |
| 116 | + mlx5_core_err(priv->mdev, "PSP failed to register due to %pe\n", |
| 117 | + priv->psp->psp); |
| 118 | +} |
| 119 | + |
| 120 | +int mlx5e_psp_init(struct mlx5e_priv *priv) |
| 121 | +{ |
| 122 | + struct mlx5_core_dev *mdev = priv->mdev; |
| 123 | + struct mlx5e_psp *psp; |
| 124 | + |
| 125 | + if (!mlx5_is_psp_device(mdev)) { |
| 126 | + mlx5_core_dbg(mdev, "PSP offload not supported\n"); |
| 127 | + return -EOPNOTSUPP; |
| 128 | + } |
| 129 | + |
| 130 | + if (!MLX5_CAP_ETH(mdev, swp)) { |
| 131 | + mlx5_core_dbg(mdev, "SWP not supported\n"); |
| 132 | + return -EOPNOTSUPP; |
| 133 | + } |
| 134 | + |
| 135 | + if (!MLX5_CAP_ETH(mdev, swp_csum)) { |
| 136 | + mlx5_core_dbg(mdev, "SWP checksum not supported\n"); |
| 137 | + return -EOPNOTSUPP; |
| 138 | + } |
| 139 | + |
| 140 | + if (!MLX5_CAP_ETH(mdev, swp_csum_l4_partial)) { |
| 141 | + mlx5_core_dbg(mdev, "SWP L4 partial checksum not supported\n"); |
| 142 | + return -EOPNOTSUPP; |
| 143 | + } |
| 144 | + |
| 145 | + if (!MLX5_CAP_ETH(mdev, swp_lso)) { |
| 146 | + mlx5_core_dbg(mdev, "PSP LSO not supported\n"); |
| 147 | + return -EOPNOTSUPP; |
| 148 | + } |
| 149 | + |
| 150 | + psp = kzalloc(sizeof(*psp), GFP_KERNEL); |
| 151 | + if (!psp) |
| 152 | + return -ENOMEM; |
| 153 | + |
| 154 | + priv->psp = psp; |
| 155 | + mlx5_core_dbg(priv->mdev, "PSP attached to netdevice\n"); |
| 156 | + return 0; |
| 157 | +} |
| 158 | + |
| 159 | +void mlx5e_psp_cleanup(struct mlx5e_priv *priv) |
| 160 | +{ |
| 161 | + struct mlx5e_psp *psp = priv->psp; |
| 162 | + |
| 163 | + if (!psp) |
| 164 | + return; |
| 165 | + |
| 166 | + priv->psp = NULL; |
| 167 | + kfree(psp); |
| 168 | +} |
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