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| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | +%YAML 1.2 |
| 3 | +--- |
| 4 | +$id: http://devicetree.org/schemas/sound/everest,es8326.yaml# |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | + |
| 7 | +title: Everest ES8326 audio CODEC |
| 8 | + |
| 9 | +maintainers: |
| 10 | + - David Yang <yangxiaohua@everest-semi.com> |
| 11 | + |
| 12 | +properties: |
| 13 | + compatible: |
| 14 | + const: everest,es8326 |
| 15 | + |
| 16 | + reg: |
| 17 | + maxItems: 1 |
| 18 | + |
| 19 | + clocks: |
| 20 | + items: |
| 21 | + - description: clock for master clock (MCLK) |
| 22 | + |
| 23 | + clock-names: |
| 24 | + items: |
| 25 | + - const: mclk |
| 26 | + |
| 27 | + "#sound-dai-cells": |
| 28 | + const: 0 |
| 29 | + |
| 30 | + everest,jack-pol: |
| 31 | + $ref: /schemas/types.yaml#/definitions/uint8 |
| 32 | + description: | |
| 33 | + just the value of reg 57. Bit(3) decides whether the jack polarity is inverted. |
| 34 | + Bit(2) decides whether the button on the headset is inverted. |
| 35 | + Bit(1)/(0) decides the mic properity to be OMTP/CTIA or auto. |
| 36 | + minimum: 0x00 |
| 37 | + maximum: 0x0f |
| 38 | + default: 0x0f |
| 39 | + |
| 40 | + everest,mic1-src: |
| 41 | + $ref: /schemas/types.yaml#/definitions/uint8 |
| 42 | + description: |
| 43 | + the value of reg 2A when headset plugged. |
| 44 | + minimum: 0x00 |
| 45 | + maximum: 0x77 |
| 46 | + default: 0x22 |
| 47 | + |
| 48 | + everest,mic2-src: |
| 49 | + $ref: /schemas/types.yaml#/definitions/uint8 |
| 50 | + description: |
| 51 | + the value of reg 2A when headset unplugged. |
| 52 | + minimum: 0x00 |
| 53 | + maximum: 0x77 |
| 54 | + default: 0x44 |
| 55 | + |
| 56 | + everest,jack-detect-inverted: |
| 57 | + $ref: /schemas/types.yaml#/definitions/flag |
| 58 | + description: |
| 59 | + Defined to invert the jack detection. |
| 60 | + |
| 61 | + everest,interrupt-src: |
| 62 | + $ref: /schemas/types.yaml#/definitions/uint8 |
| 63 | + description: | |
| 64 | + value of reg 0x58, Defines the interrupt source. |
| 65 | + Bit(2) 1 means button press triggers irq, 0 means not. |
| 66 | + Bit(3) 1 means PIN9 is the irq source for jack detection. When set to 0, |
| 67 | + bias change on PIN9 do not triggers irq. |
| 68 | + Bit(4) 1 means PIN27 is the irq source for jack detection. |
| 69 | + Bit(5) 1 means PIN9 is the irq source after MIC detect. |
| 70 | + Bit(6) 1 means PIN27 is the irq source after MIC detect. |
| 71 | + minimum: 0 |
| 72 | + maximum: 0x3c |
| 73 | + default: 0x08 |
| 74 | + |
| 75 | + everest,interrupt-clk: |
| 76 | + $ref: /schemas/types.yaml#/definitions/uint8 |
| 77 | + description: | |
| 78 | + value of reg 0x59, Defines the interrupt output behavior. |
| 79 | + Bit(0-3) 0 means irq pulse equals 512*internal clock |
| 80 | + 1 means irq pulse equals 1024*internal clock |
| 81 | + 2 means ... |
| 82 | + 7 means irq pulse equals 65536*internal clock |
| 83 | + 8 means irq mutes PA |
| 84 | + 9 means irq mutes PA and DAC output |
| 85 | + Bit(4) 1 means we invert the interrupt output. |
| 86 | + Bit(6) 1 means the chip do not detect jack type after button released. |
| 87 | + 0 means the chip detect jack type again after button released. |
| 88 | + minimum: 0 |
| 89 | + maximum: 0x7f |
| 90 | + default: 0x45 |
| 91 | + |
| 92 | +required: |
| 93 | + - compatible |
| 94 | + - reg |
| 95 | + - "#sound-dai-cells" |
| 96 | + |
| 97 | +additionalProperties: false |
| 98 | + |
| 99 | +examples: |
| 100 | + - | |
| 101 | + i2c { |
| 102 | + #address-cells = <1>; |
| 103 | + #size-cells = <0>; |
| 104 | + es8326: codec@19 { |
| 105 | + compatible = "everest,es8326"; |
| 106 | + reg = <0x19>; |
| 107 | + clocks = <&clks 10>; |
| 108 | + clock-names = "mclk"; |
| 109 | + #sound-dai-cells = <0>; |
| 110 | + everest,mic1-src = [22]; |
| 111 | + everest,mic2-src = [44]; |
| 112 | + everest,jack-pol = [0e]; |
| 113 | + everest,interrupt-src = [08]; |
| 114 | + everest,interrupt-clk = [45]; |
| 115 | + }; |
| 116 | + }; |
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