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torvaldstorvalds
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Merge tag 'dmaengine-fix-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
Pull dmaengine fixes from Vinod Koul: - A bunch of dw driver changes to fix the src/dst addr width config - Omap driver fix for sglen initialization - stm32-dma3 driver lli_size init fix - dw edma driver fixes for watermark interrupts and unmasking STOP and ABORT interrupts * tag 'dmaengine-fix-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: dmaengine: dw-edma: Do not enable watermark interrupts for HDMA dmaengine: dw-edma: Fix unmasking STOP and ABORT interrupts for HDMA dmaengine: stm32-dma3: Set lli_size after allocation dmaengine: ti: omap-dma: Initialize sglen after allocation dmaengine: dw: Unify ret-val local variables naming dmaengine: dw: Simplify max-burst calculation procedure dmaengine: dw: Define encode_maxburst() above prepare_ctllo() callbacks dmaengine: dw: Simplify prepare CTL_LO methods dmaengine: dw: Add memory bus width verification dmaengine: dw: Add peripheral bus width verification
2 parents 32fafaf + 9f646ff commit 922842a

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8 files changed

+166
-79
lines changed

8 files changed

+166
-79
lines changed

‎drivers/dma/dw-edma/dw-hdma-v0-core.c‎

Lines changed: 8 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -17,8 +17,8 @@ enum dw_hdma_control {
1717
DW_HDMA_V0_CB = BIT(0),
1818
DW_HDMA_V0_TCB = BIT(1),
1919
DW_HDMA_V0_LLP = BIT(2),
20-
DW_HDMA_V0_LIE = BIT(3),
21-
DW_HDMA_V0_RIE = BIT(4),
20+
DW_HDMA_V0_LWIE = BIT(3),
21+
DW_HDMA_V0_RWIE = BIT(4),
2222
DW_HDMA_V0_CCS = BIT(8),
2323
DW_HDMA_V0_LLE = BIT(9),
2424
};
@@ -195,25 +195,14 @@ static void dw_hdma_v0_write_ll_link(struct dw_edma_chunk *chunk,
195195
static void dw_hdma_v0_core_write_chunk(struct dw_edma_chunk *chunk)
196196
{
197197
struct dw_edma_burst *child;
198-
struct dw_edma_chan *chan = chunk->chan;
199198
u32 control = 0, i = 0;
200-
int j;
201199

202200
if (chunk->cb)
203201
control = DW_HDMA_V0_CB;
204202

205-
j = chunk->bursts_alloc;
206-
list_for_each_entry(child, &chunk->burst->list, list) {
207-
j--;
208-
if (!j) {
209-
control |= DW_HDMA_V0_LIE;
210-
if (!(chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL))
211-
control |= DW_HDMA_V0_RIE;
212-
}
213-
203+
list_for_each_entry(child, &chunk->burst->list, list)
214204
dw_hdma_v0_write_ll_data(chunk, i++, control, child->sz,
215205
child->sar, child->dar);
216-
}
217206

218207
control = DW_HDMA_V0_LLP | DW_HDMA_V0_TCB;
219208
if (!chunk->cb)
@@ -247,10 +236,11 @@ static void dw_hdma_v0_core_start(struct dw_edma_chunk *chunk, bool first)
247236
if (first) {
248237
/* Enable engine */
249238
SET_CH_32(dw, chan->dir, chan->id, ch_en, BIT(0));
250-
/* Interrupt enable&unmask - done, abort */
251-
tmp = GET_CH_32(dw, chan->dir, chan->id, int_setup) |
252-
HDMA_V0_STOP_INT_MASK | HDMA_V0_ABORT_INT_MASK |
253-
HDMA_V0_LOCAL_STOP_INT_EN | HDMA_V0_LOCAL_ABORT_INT_EN;
239+
/* Interrupt unmask - stop, abort */
240+
tmp = GET_CH_32(dw, chan->dir, chan->id, int_setup);
241+
tmp &= ~(HDMA_V0_STOP_INT_MASK | HDMA_V0_ABORT_INT_MASK);
242+
/* Interrupt enable - stop, abort */
243+
tmp |= HDMA_V0_LOCAL_STOP_INT_EN | HDMA_V0_LOCAL_ABORT_INT_EN;
254244
if (!(dw->chip->flags & DW_EDMA_CHIP_LOCAL))
255245
tmp |= HDMA_V0_REMOTE_STOP_INT_EN | HDMA_V0_REMOTE_ABORT_INT_EN;
256246
SET_CH_32(dw, chan->dir, chan->id, int_setup, tmp);

‎drivers/dma/dw/core.c‎

Lines changed: 109 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@
1616
#include <linux/init.h>
1717
#include <linux/interrupt.h>
1818
#include <linux/io.h>
19+
#include <linux/log2.h>
1920
#include <linux/mm.h>
2021
#include <linux/module.h>
2122
#include <linux/slab.h>
@@ -621,12 +622,10 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
621622
struct dw_desc *prev;
622623
struct dw_desc *first;
623624
u32 ctllo, ctlhi;
624-
u8 m_master = dwc->dws.m_master;
625-
u8 lms = DWC_LLP_LMS(m_master);
625+
u8 lms = DWC_LLP_LMS(dwc->dws.m_master);
626626
dma_addr_t reg;
627627
unsigned int reg_width;
628628
unsigned int mem_width;
629-
unsigned int data_width = dw->pdata->data_width[m_master];
630629
unsigned int i;
631630
struct scatterlist *sg;
632631
size_t total_len = 0;
@@ -660,7 +659,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
660659
mem = sg_dma_address(sg);
661660
len = sg_dma_len(sg);
662661

663-
mem_width = __ffs(data_width | mem | len);
662+
mem_width = __ffs(sconfig->src_addr_width | mem | len);
664663

665664
slave_sg_todev_fill_desc:
666665
desc = dwc_desc_get(dwc);
@@ -720,7 +719,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
720719
lli_write(desc, sar, reg);
721720
lli_write(desc, dar, mem);
722721
lli_write(desc, ctlhi, ctlhi);
723-
mem_width = __ffs(data_width | mem);
722+
mem_width = __ffs(sconfig->dst_addr_width | mem);
724723
lli_write(desc, ctllo, ctllo | DWC_CTLL_DST_WIDTH(mem_width));
725724
desc->len = dlen;
726725

@@ -780,20 +779,108 @@ bool dw_dma_filter(struct dma_chan *chan, void *param)
780779
}
781780
EXPORT_SYMBOL_GPL(dw_dma_filter);
782781

783-
static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
782+
static int dwc_verify_maxburst(struct dma_chan *chan)
784783
{
785784
struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
786-
struct dw_dma *dw = to_dw_dma(chan->device);
787785

788-
memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
786+
dwc->dma_sconfig.src_maxburst =
787+
clamp(dwc->dma_sconfig.src_maxburst, 1U, dwc->max_burst);
788+
dwc->dma_sconfig.dst_maxburst =
789+
clamp(dwc->dma_sconfig.dst_maxburst, 1U, dwc->max_burst);
789790

790791
dwc->dma_sconfig.src_maxburst =
791-
clamp(dwc->dma_sconfig.src_maxburst, 0U, dwc->max_burst);
792+
rounddown_pow_of_two(dwc->dma_sconfig.src_maxburst);
792793
dwc->dma_sconfig.dst_maxburst =
793-
clamp(dwc->dma_sconfig.dst_maxburst, 0U, dwc->max_burst);
794+
rounddown_pow_of_two(dwc->dma_sconfig.dst_maxburst);
794795

795-
dw->encode_maxburst(dwc, &dwc->dma_sconfig.src_maxburst);
796-
dw->encode_maxburst(dwc, &dwc->dma_sconfig.dst_maxburst);
796+
return 0;
797+
}
798+
799+
static int dwc_verify_p_buswidth(struct dma_chan *chan)
800+
{
801+
struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
802+
struct dw_dma *dw = to_dw_dma(chan->device);
803+
u32 reg_width, max_width;
804+
805+
if (dwc->dma_sconfig.direction == DMA_MEM_TO_DEV)
806+
reg_width = dwc->dma_sconfig.dst_addr_width;
807+
else if (dwc->dma_sconfig.direction == DMA_DEV_TO_MEM)
808+
reg_width = dwc->dma_sconfig.src_addr_width;
809+
else /* DMA_MEM_TO_MEM */
810+
return 0;
811+
812+
max_width = dw->pdata->data_width[dwc->dws.p_master];
813+
814+
/* Fall-back to 1-byte transfer width if undefined */
815+
if (reg_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
816+
reg_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
817+
else if (!is_power_of_2(reg_width) || reg_width > max_width)
818+
return -EINVAL;
819+
else /* bus width is valid */
820+
return 0;
821+
822+
/* Update undefined addr width value */
823+
if (dwc->dma_sconfig.direction == DMA_MEM_TO_DEV)
824+
dwc->dma_sconfig.dst_addr_width = reg_width;
825+
else /* DMA_DEV_TO_MEM */
826+
dwc->dma_sconfig.src_addr_width = reg_width;
827+
828+
return 0;
829+
}
830+
831+
static int dwc_verify_m_buswidth(struct dma_chan *chan)
832+
{
833+
struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
834+
struct dw_dma *dw = to_dw_dma(chan->device);
835+
u32 reg_width, reg_burst, mem_width;
836+
837+
mem_width = dw->pdata->data_width[dwc->dws.m_master];
838+
839+
/*
840+
* It's possible to have a data portion locked in the DMA FIFO in case
841+
* of the channel suspension. Subsequent channel disabling will cause
842+
* that data silent loss. In order to prevent that maintain the src and
843+
* dst transfer widths coherency by means of the relation:
844+
* (CTLx.SRC_TR_WIDTH * CTLx.SRC_MSIZE >= CTLx.DST_TR_WIDTH)
845+
* Look for the details in the commit message that brings this change.
846+
*
847+
* Note the DMA configs utilized in the calculations below must have
848+
* been verified to have correct values by this method call.
849+
*/
850+
if (dwc->dma_sconfig.direction == DMA_MEM_TO_DEV) {
851+
reg_width = dwc->dma_sconfig.dst_addr_width;
852+
if (mem_width < reg_width)
853+
return -EINVAL;
854+
855+
dwc->dma_sconfig.src_addr_width = mem_width;
856+
} else if (dwc->dma_sconfig.direction == DMA_DEV_TO_MEM) {
857+
reg_width = dwc->dma_sconfig.src_addr_width;
858+
reg_burst = dwc->dma_sconfig.src_maxburst;
859+
860+
dwc->dma_sconfig.dst_addr_width = min(mem_width, reg_width * reg_burst);
861+
}
862+
863+
return 0;
864+
}
865+
866+
static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
867+
{
868+
struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
869+
int ret;
870+
871+
memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
872+
873+
ret = dwc_verify_maxburst(chan);
874+
if (ret)
875+
return ret;
876+
877+
ret = dwc_verify_p_buswidth(chan);
878+
if (ret)
879+
return ret;
880+
881+
ret = dwc_verify_m_buswidth(chan);
882+
if (ret)
883+
return ret;
797884

798885
return 0;
799886
}
@@ -1068,7 +1155,7 @@ int do_dma_probe(struct dw_dma_chip *chip)
10681155
bool autocfg = false;
10691156
unsigned int dw_params;
10701157
unsigned int i;
1071-
int err;
1158+
int ret;
10721159

10731160
dw->pdata = devm_kzalloc(chip->dev, sizeof(*dw->pdata), GFP_KERNEL);
10741161
if (!dw->pdata)
@@ -1084,7 +1171,7 @@ int do_dma_probe(struct dw_dma_chip *chip)
10841171

10851172
autocfg = dw_params >> DW_PARAMS_EN & 1;
10861173
if (!autocfg) {
1087-
err = -EINVAL;
1174+
ret = -EINVAL;
10881175
goto err_pdata;
10891176
}
10901177

@@ -1104,7 +1191,7 @@ int do_dma_probe(struct dw_dma_chip *chip)
11041191
pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
11051192
pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
11061193
} else if (chip->pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) {
1107-
err = -EINVAL;
1194+
ret = -EINVAL;
11081195
goto err_pdata;
11091196
} else {
11101197
memcpy(dw->pdata, chip->pdata, sizeof(*dw->pdata));
@@ -1116,7 +1203,7 @@ int do_dma_probe(struct dw_dma_chip *chip)
11161203
dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan),
11171204
GFP_KERNEL);
11181205
if (!dw->chan) {
1119-
err = -ENOMEM;
1206+
ret = -ENOMEM;
11201207
goto err_pdata;
11211208
}
11221209

@@ -1134,15 +1221,15 @@ int do_dma_probe(struct dw_dma_chip *chip)
11341221
sizeof(struct dw_desc), 4, 0);
11351222
if (!dw->desc_pool) {
11361223
dev_err(chip->dev, "No memory for descriptors dma pool\n");
1137-
err = -ENOMEM;
1224+
ret = -ENOMEM;
11381225
goto err_pdata;
11391226
}
11401227

11411228
tasklet_setup(&dw->tasklet, dw_dma_tasklet);
11421229

1143-
err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED,
1230+
ret = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED,
11441231
dw->name, dw);
1145-
if (err)
1232+
if (ret)
11461233
goto err_pdata;
11471234

11481235
INIT_LIST_HEAD(&dw->dma.channels);
@@ -1254,8 +1341,8 @@ int do_dma_probe(struct dw_dma_chip *chip)
12541341
*/
12551342
dma_set_max_seg_size(dw->dma.dev, dw->chan[0].block_size);
12561343

1257-
err = dma_async_device_register(&dw->dma);
1258-
if (err)
1344+
ret = dma_async_device_register(&dw->dma);
1345+
if (ret)
12591346
goto err_dma_register;
12601347

12611348
dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n",
@@ -1269,7 +1356,7 @@ int do_dma_probe(struct dw_dma_chip *chip)
12691356
free_irq(chip->irq, dw);
12701357
err_pdata:
12711358
pm_runtime_put_sync_suspend(chip->dev);
1272-
return err;
1359+
return ret;
12731360
}
12741361

12751362
int do_dma_remove(struct dw_dma_chip *chip)

‎drivers/dma/dw/dw.c‎

Lines changed: 24 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -64,30 +64,39 @@ static size_t dw_dma_block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width)
6464
return DWC_CTLH_BLOCK_TS(block) << width;
6565
}
6666

67+
static inline u8 dw_dma_encode_maxburst(u32 maxburst)
68+
{
69+
/*
70+
* Fix burst size according to dw_dmac. We need to convert them as:
71+
* 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
72+
*/
73+
return maxburst > 1 ? fls(maxburst) - 2 : 0;
74+
}
75+
6776
static u32 dw_dma_prepare_ctllo(struct dw_dma_chan *dwc)
6877
{
6978
struct dma_slave_config *sconfig = &dwc->dma_sconfig;
70-
u8 smsize = (dwc->direction == DMA_DEV_TO_MEM) ? sconfig->src_maxburst : 0;
71-
u8 dmsize = (dwc->direction == DMA_MEM_TO_DEV) ? sconfig->dst_maxburst : 0;
72-
u8 p_master = dwc->dws.p_master;
73-
u8 m_master = dwc->dws.m_master;
74-
u8 dms = (dwc->direction == DMA_MEM_TO_DEV) ? p_master : m_master;
75-
u8 sms = (dwc->direction == DMA_DEV_TO_MEM) ? p_master : m_master;
79+
u8 smsize = 0, dmsize = 0;
80+
u8 sms, dms;
81+
82+
if (dwc->direction == DMA_MEM_TO_DEV) {
83+
sms = dwc->dws.m_master;
84+
dms = dwc->dws.p_master;
85+
dmsize = dw_dma_encode_maxburst(sconfig->dst_maxburst);
86+
} else if (dwc->direction == DMA_DEV_TO_MEM) {
87+
sms = dwc->dws.p_master;
88+
dms = dwc->dws.m_master;
89+
smsize = dw_dma_encode_maxburst(sconfig->src_maxburst);
90+
} else /* DMA_MEM_TO_MEM */ {
91+
sms = dwc->dws.m_master;
92+
dms = dwc->dws.m_master;
93+
}
7694

7795
return DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN |
7896
DWC_CTLL_DST_MSIZE(dmsize) | DWC_CTLL_SRC_MSIZE(smsize) |
7997
DWC_CTLL_DMS(dms) | DWC_CTLL_SMS(sms);
8098
}
8199

82-
static void dw_dma_encode_maxburst(struct dw_dma_chan *dwc, u32 *maxburst)
83-
{
84-
/*
85-
* Fix burst size according to dw_dmac. We need to convert them as:
86-
* 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
87-
*/
88-
*maxburst = *maxburst > 1 ? fls(*maxburst) - 2 : 0;
89-
}
90-
91100
static void dw_dma_set_device_name(struct dw_dma *dw, int id)
92101
{
93102
snprintf(dw->name, sizeof(dw->name), "dw:dmac%d", id);
@@ -116,7 +125,6 @@ int dw_dma_probe(struct dw_dma_chip *chip)
116125
dw->suspend_chan = dw_dma_suspend_chan;
117126
dw->resume_chan = dw_dma_resume_chan;
118127
dw->prepare_ctllo = dw_dma_prepare_ctllo;
119-
dw->encode_maxburst = dw_dma_encode_maxburst;
120128
dw->bytes2block = dw_dma_bytes2block;
121129
dw->block2bytes = dw_dma_block2bytes;
122130

‎drivers/dma/dw/idma32.c‎

Lines changed: 11 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -199,21 +199,25 @@ static size_t idma32_block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width)
199199
return IDMA32C_CTLH_BLOCK_TS(block);
200200
}
201201

202+
static inline u8 idma32_encode_maxburst(u32 maxburst)
203+
{
204+
return maxburst > 1 ? fls(maxburst) - 1 : 0;
205+
}
206+
202207
static u32 idma32_prepare_ctllo(struct dw_dma_chan *dwc)
203208
{
204209
struct dma_slave_config *sconfig = &dwc->dma_sconfig;
205-
u8 smsize = (dwc->direction == DMA_DEV_TO_MEM) ? sconfig->src_maxburst : 0;
206-
u8 dmsize = (dwc->direction == DMA_MEM_TO_DEV) ? sconfig->dst_maxburst : 0;
210+
u8 smsize = 0, dmsize = 0;
211+
212+
if (dwc->direction == DMA_MEM_TO_DEV)
213+
dmsize = idma32_encode_maxburst(sconfig->dst_maxburst);
214+
else if (dwc->direction == DMA_DEV_TO_MEM)
215+
smsize = idma32_encode_maxburst(sconfig->src_maxburst);
207216

208217
return DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN |
209218
DWC_CTLL_DST_MSIZE(dmsize) | DWC_CTLL_SRC_MSIZE(smsize);
210219
}
211220

212-
static void idma32_encode_maxburst(struct dw_dma_chan *dwc, u32 *maxburst)
213-
{
214-
*maxburst = *maxburst > 1 ? fls(*maxburst) - 1 : 0;
215-
}
216-
217221
static void idma32_set_device_name(struct dw_dma *dw, int id)
218222
{
219223
snprintf(dw->name, sizeof(dw->name), "idma32:dmac%d", id);
@@ -270,7 +274,6 @@ int idma32_dma_probe(struct dw_dma_chip *chip)
270274
dw->suspend_chan = idma32_suspend_chan;
271275
dw->resume_chan = idma32_resume_chan;
272276
dw->prepare_ctllo = idma32_prepare_ctllo;
273-
dw->encode_maxburst = idma32_encode_maxburst;
274277
dw->bytes2block = idma32_bytes2block;
275278
dw->block2bytes = idma32_block2bytes;
276279

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