Skip to content

Commit 97278f8

Browse files
oleremdavem330
olerem
authored and
davem330
committed
net: dsa: microchip: add IPV information support
Most of Microchip KSZ switches use Internal Priority Value associated with every frame. For example, it is possible to map any VLAN PCP or DSCP value to IPV and at the end, map IPV to a queue. Since amount of IPVs is not equal to amount of queues, add this information and make use of it in some functions. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Acked-by: Arun Ramadoss <arun.ramadoss@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
1 parent 96c6f33 commit 97278f8

File tree

2 files changed

+20
-3
lines changed

2 files changed

+20
-3
lines changed

‎drivers/net/dsa/microchip/ksz_common.c‎

Lines changed: 19 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1225,6 +1225,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
12251225
.port_cnt = 3, /* total port count */
12261226
.port_nirqs = 3,
12271227
.num_tx_queues = 4,
1228+
.num_ipvs = 8,
12281229
.tc_cbs_supported = true,
12291230
.tc_ets_supported = true,
12301231
.ops = &ksz9477_dev_ops,
@@ -1255,6 +1256,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
12551256
.cpu_ports = 0x10, /* can be configured as cpu port */
12561257
.port_cnt = 5, /* total cpu and user ports */
12571258
.num_tx_queues = 4,
1259+
.num_ipvs = 4,
12581260
.ops = &ksz8_dev_ops,
12591261
.phylink_mac_ops = &ksz8_phylink_mac_ops,
12601262
.ksz87xx_eee_link_erratum = true,
@@ -1295,6 +1297,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
12951297
.cpu_ports = 0x10, /* can be configured as cpu port */
12961298
.port_cnt = 5, /* total cpu and user ports */
12971299
.num_tx_queues = 4,
1300+
.num_ipvs = 4,
12981301
.ops = &ksz8_dev_ops,
12991302
.phylink_mac_ops = &ksz8_phylink_mac_ops,
13001303
.ksz87xx_eee_link_erratum = true,
@@ -1321,6 +1324,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
13211324
.cpu_ports = 0x10, /* can be configured as cpu port */
13221325
.port_cnt = 5, /* total cpu and user ports */
13231326
.num_tx_queues = 4,
1327+
.num_ipvs = 4,
13241328
.ops = &ksz8_dev_ops,
13251329
.phylink_mac_ops = &ksz8_phylink_mac_ops,
13261330
.ksz87xx_eee_link_erratum = true,
@@ -1347,6 +1351,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
13471351
.cpu_ports = 0x4, /* can be configured as cpu port */
13481352
.port_cnt = 3,
13491353
.num_tx_queues = 4,
1354+
.num_ipvs = 4,
13501355
.ops = &ksz8_dev_ops,
13511356
.phylink_mac_ops = &ksz8830_phylink_mac_ops,
13521357
.mib_names = ksz88xx_mib_names,
@@ -1372,6 +1377,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
13721377
.port_cnt = 7, /* total physical port count */
13731378
.port_nirqs = 4,
13741379
.num_tx_queues = 4,
1380+
.num_ipvs = 8,
13751381
.tc_cbs_supported = true,
13761382
.tc_ets_supported = true,
13771383
.ops = &ksz9477_dev_ops,
@@ -1407,6 +1413,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
14071413
.port_cnt = 6, /* total physical port count */
14081414
.port_nirqs = 2,
14091415
.num_tx_queues = 4,
1416+
.num_ipvs = 8,
14101417
.ops = &ksz9477_dev_ops,
14111418
.phylink_mac_ops = &ksz9477_phylink_mac_ops,
14121419
.mib_names = ksz9477_mib_names,
@@ -1440,6 +1447,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
14401447
.port_cnt = 7, /* total physical port count */
14411448
.port_nirqs = 2,
14421449
.num_tx_queues = 4,
1450+
.num_ipvs = 8,
14431451
.ops = &ksz9477_dev_ops,
14441452
.phylink_mac_ops = &ksz9477_phylink_mac_ops,
14451453
.mib_names = ksz9477_mib_names,
@@ -1471,6 +1479,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
14711479
.port_cnt = 3, /* total port count */
14721480
.port_nirqs = 2,
14731481
.num_tx_queues = 4,
1482+
.num_ipvs = 8,
14741483
.ops = &ksz9477_dev_ops,
14751484
.phylink_mac_ops = &ksz9477_phylink_mac_ops,
14761485
.mib_names = ksz9477_mib_names,
@@ -1498,6 +1507,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
14981507
.port_cnt = 3, /* total port count */
14991508
.port_nirqs = 3,
15001509
.num_tx_queues = 4,
1510+
.num_ipvs = 8,
15011511
.tc_cbs_supported = true,
15021512
.tc_ets_supported = true,
15031513
.ops = &ksz9477_dev_ops,
@@ -1527,6 +1537,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
15271537
.port_cnt = 7, /* total port count */
15281538
.port_nirqs = 3,
15291539
.num_tx_queues = 4,
1540+
.num_ipvs = 8,
15301541
.tc_cbs_supported = true,
15311542
.tc_ets_supported = true,
15321543
.ops = &ksz9477_dev_ops,
@@ -1561,6 +1572,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
15611572
.port_cnt = 7, /* total physical port count */
15621573
.port_nirqs = 3,
15631574
.num_tx_queues = 4,
1575+
.num_ipvs = 8,
15641576
.tc_cbs_supported = true,
15651577
.tc_ets_supported = true,
15661578
.ops = &ksz9477_dev_ops,
@@ -1593,6 +1605,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
15931605
.port_cnt = 5, /* total physical port count */
15941606
.port_nirqs = 6,
15951607
.num_tx_queues = 8,
1608+
.num_ipvs = 8,
15961609
.tc_cbs_supported = true,
15971610
.tc_ets_supported = true,
15981611
.ops = &lan937x_dev_ops,
@@ -1621,6 +1634,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
16211634
.port_cnt = 6, /* total physical port count */
16221635
.port_nirqs = 6,
16231636
.num_tx_queues = 8,
1637+
.num_ipvs = 8,
16241638
.tc_cbs_supported = true,
16251639
.tc_ets_supported = true,
16261640
.ops = &lan937x_dev_ops,
@@ -1649,6 +1663,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
16491663
.port_cnt = 8, /* total physical port count */
16501664
.port_nirqs = 6,
16511665
.num_tx_queues = 8,
1666+
.num_ipvs = 8,
16521667
.tc_cbs_supported = true,
16531668
.tc_ets_supported = true,
16541669
.ops = &lan937x_dev_ops,
@@ -1681,6 +1696,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
16811696
.port_cnt = 5, /* total physical port count */
16821697
.port_nirqs = 6,
16831698
.num_tx_queues = 8,
1699+
.num_ipvs = 8,
16841700
.tc_cbs_supported = true,
16851701
.tc_ets_supported = true,
16861702
.ops = &lan937x_dev_ops,
@@ -1713,6 +1729,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
17131729
.port_cnt = 8, /* total physical port count */
17141730
.port_nirqs = 6,
17151731
.num_tx_queues = 8,
1732+
.num_ipvs = 8,
17161733
.tc_cbs_supported = true,
17171734
.tc_ets_supported = true,
17181735
.ops = &lan937x_dev_ops,
@@ -3565,7 +3582,7 @@ static int ksz_tc_ets_add(struct ksz_device *dev, int port,
35653582
for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) {
35663583
int queue;
35673584

3568-
if (tc_prio > KSZ9477_MAX_TC_PRIO)
3585+
if (tc_prio >= dev->info->num_ipvs)
35693586
break;
35703587

35713588
queue = ksz_ets_band_to_queue(p, p->priomap[tc_prio]);
@@ -3607,7 +3624,7 @@ static int ksz_tc_ets_del(struct ksz_device *dev, int port)
36073624
/* Revert the queue mapping for TC-priority to its default setting on
36083625
* the chip.
36093626
*/
3610-
for (tc_prio = 0; tc_prio <= KSZ9477_MAX_TC_PRIO; tc_prio++) {
3627+
for (tc_prio = 0; tc_prio < dev->info->num_ipvs; tc_prio++) {
36113628
int queue;
36123629

36133630
queue = tc_prio >> s;

‎drivers/net/dsa/microchip/ksz_common.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -59,6 +59,7 @@ struct ksz_chip_data {
5959
int port_cnt;
6060
u8 port_nirqs;
6161
u8 num_tx_queues;
62+
u8 num_ipvs; /* number of Internal Priority Values */
6263
bool tc_cbs_supported;
6364
bool tc_ets_supported;
6465
const struct ksz_dev_ops *ops;
@@ -721,7 +722,6 @@ static inline int is_lan937x(struct ksz_device *dev)
721722
#define KSZ9477_PORT_MRI_TC_MAP__4 0x0808
722723

723724
#define KSZ9477_PORT_TC_MAP_S 4
724-
#define KSZ9477_MAX_TC_PRIO 7
725725

726726
/* CBS related registers */
727727
#define REG_PORT_MTI_QUEUE_INDEX__4 0x0900

0 commit comments

Comments
 (0)