@@ -361,6 +361,222 @@ int mtk_afe_dai_resume(struct snd_soc_dai *dai)
361361}
362362EXPORT_SYMBOL_GPL (mtk_afe_dai_resume );
363363
364+ int mtk_memif_set_enable (struct mtk_base_afe * afe , int id )
365+ {
366+ struct mtk_base_afe_memif * memif = & afe -> memif [id ];
367+
368+ if (memif -> data -> enable_shift < 0 ) {
369+ dev_warn (afe -> dev , "%s(), error, id %d, enable_shift < 0\n" ,
370+ __func__ , id );
371+ return 0 ;
372+ }
373+ return mtk_regmap_update_bits (afe -> regmap , memif -> data -> enable_reg ,
374+ 1 , 1 , memif -> data -> enable_shift );
375+ }
376+ EXPORT_SYMBOL_GPL (mtk_memif_set_enable );
377+
378+ int mtk_memif_set_disable (struct mtk_base_afe * afe , int id )
379+ {
380+ struct mtk_base_afe_memif * memif = & afe -> memif [id ];
381+
382+ if (memif -> data -> enable_shift < 0 ) {
383+ dev_warn (afe -> dev , "%s(), error, id %d, enable_shift < 0\n" ,
384+ __func__ , id );
385+ return 0 ;
386+ }
387+ return mtk_regmap_update_bits (afe -> regmap , memif -> data -> enable_reg ,
388+ 1 , 0 , memif -> data -> enable_shift );
389+ }
390+ EXPORT_SYMBOL_GPL (mtk_memif_set_disable );
391+
392+ int mtk_memif_set_addr (struct mtk_base_afe * afe , int id ,
393+ unsigned char * dma_area ,
394+ dma_addr_t dma_addr ,
395+ size_t dma_bytes )
396+ {
397+ struct mtk_base_afe_memif * memif = & afe -> memif [id ];
398+ int msb_at_bit33 = upper_32_bits (dma_addr ) ? 1 : 0 ;
399+ unsigned int phys_buf_addr = lower_32_bits (dma_addr );
400+ unsigned int phys_buf_addr_upper_32 = upper_32_bits (dma_addr );
401+
402+ memif -> dma_area = dma_area ;
403+ memif -> dma_addr = dma_addr ;
404+ memif -> dma_bytes = dma_bytes ;
405+
406+ /* start */
407+ mtk_regmap_write (afe -> regmap , memif -> data -> reg_ofs_base ,
408+ phys_buf_addr );
409+ /* end */
410+ if (memif -> data -> reg_ofs_end )
411+ mtk_regmap_write (afe -> regmap ,
412+ memif -> data -> reg_ofs_end ,
413+ phys_buf_addr + dma_bytes - 1 );
414+ else
415+ mtk_regmap_write (afe -> regmap ,
416+ memif -> data -> reg_ofs_base +
417+ AFE_BASE_END_OFFSET ,
418+ phys_buf_addr + dma_bytes - 1 );
419+
420+ /* set start, end, upper 32 bits */
421+ if (memif -> data -> reg_ofs_base_msb ) {
422+ mtk_regmap_write (afe -> regmap , memif -> data -> reg_ofs_base_msb ,
423+ phys_buf_addr_upper_32 );
424+ mtk_regmap_write (afe -> regmap ,
425+ memif -> data -> reg_ofs_end_msb ,
426+ phys_buf_addr_upper_32 );
427+ }
428+
429+ /* set MSB to 33-bit */
430+ if (memif -> data -> msb_reg >= 0 )
431+ mtk_regmap_update_bits (afe -> regmap , memif -> data -> msb_reg ,
432+ 1 , msb_at_bit33 , memif -> data -> msb_shift );
433+
434+ return 0 ;
435+ }
436+ EXPORT_SYMBOL_GPL (mtk_memif_set_addr );
437+
438+ int mtk_memif_set_channel (struct mtk_base_afe * afe ,
439+ int id , unsigned int channel )
440+ {
441+ struct mtk_base_afe_memif * memif = & afe -> memif [id ];
442+ unsigned int mono ;
443+
444+ if (memif -> data -> mono_shift < 0 )
445+ return 0 ;
446+
447+ if (memif -> data -> quad_ch_mask ) {
448+ unsigned int quad_ch = (channel == 4 ) ? 1 : 0 ;
449+
450+ mtk_regmap_update_bits (afe -> regmap , memif -> data -> quad_ch_reg ,
451+ memif -> data -> quad_ch_mask ,
452+ quad_ch , memif -> data -> quad_ch_shift );
453+ }
454+
455+ if (memif -> data -> mono_invert )
456+ mono = (channel == 1 ) ? 0 : 1 ;
457+ else
458+ mono = (channel == 1 ) ? 1 : 0 ;
459+
460+ return mtk_regmap_update_bits (afe -> regmap , memif -> data -> mono_reg ,
461+ 1 , mono , memif -> data -> mono_shift );
462+ }
463+ EXPORT_SYMBOL_GPL (mtk_memif_set_channel );
464+
465+ static int mtk_memif_set_rate_fs (struct mtk_base_afe * afe ,
466+ int id , int fs )
467+ {
468+ struct mtk_base_afe_memif * memif = & afe -> memif [id ];
469+
470+ if (memif -> data -> fs_shift >= 0 )
471+ mtk_regmap_update_bits (afe -> regmap , memif -> data -> fs_reg ,
472+ memif -> data -> fs_maskbit ,
473+ fs , memif -> data -> fs_shift );
474+
475+ return 0 ;
476+ }
477+
478+ int mtk_memif_set_rate (struct mtk_base_afe * afe ,
479+ int id , unsigned int rate )
480+ {
481+ int fs = 0 ;
482+
483+ if (!afe -> get_dai_fs ) {
484+ dev_err (afe -> dev , "%s(), error, afe->get_dai_fs == NULL\n" ,
485+ __func__ );
486+ return - EINVAL ;
487+ }
488+
489+ fs = afe -> get_dai_fs (afe , id , rate );
490+
491+ if (fs < 0 )
492+ return - EINVAL ;
493+
494+ return mtk_memif_set_rate_fs (afe , id , fs );
495+ }
496+ EXPORT_SYMBOL_GPL (mtk_memif_set_rate );
497+
498+ int mtk_memif_set_rate_substream (struct snd_pcm_substream * substream ,
499+ int id , unsigned int rate )
500+ {
501+ struct snd_soc_pcm_runtime * rtd = substream -> private_data ;
502+ struct snd_soc_component * component =
503+ snd_soc_rtdcom_lookup (rtd , AFE_PCM_NAME );
504+ struct mtk_base_afe * afe = snd_soc_component_get_drvdata (component );
505+
506+ int fs = 0 ;
507+
508+ if (!afe -> memif_fs ) {
509+ dev_err (afe -> dev , "%s(), error, afe->memif_fs == NULL\n" ,
510+ __func__ );
511+ return - EINVAL ;
512+ }
513+
514+ fs = afe -> memif_fs (substream , rate );
515+
516+ if (fs < 0 )
517+ return - EINVAL ;
518+
519+ return mtk_memif_set_rate_fs (afe , id , fs );
520+ }
521+ EXPORT_SYMBOL_GPL (mtk_memif_set_rate_substream );
522+
523+ int mtk_memif_set_format (struct mtk_base_afe * afe ,
524+ int id , snd_pcm_format_t format )
525+ {
526+ struct mtk_base_afe_memif * memif = & afe -> memif [id ];
527+ int hd_audio = 0 ;
528+ int hd_align = 0 ;
529+
530+ /* set hd mode */
531+ switch (format ) {
532+ case SNDRV_PCM_FORMAT_S16_LE :
533+ case SNDRV_PCM_FORMAT_U16_LE :
534+ hd_audio = 0 ;
535+ break ;
536+ case SNDRV_PCM_FORMAT_S32_LE :
537+ case SNDRV_PCM_FORMAT_U32_LE :
538+ hd_audio = 1 ;
539+ hd_align = 1 ;
540+ break ;
541+ case SNDRV_PCM_FORMAT_S24_LE :
542+ case SNDRV_PCM_FORMAT_U24_LE :
543+ hd_audio = 1 ;
544+ break ;
545+ default :
546+ dev_err (afe -> dev , "%s() error: unsupported format %d\n" ,
547+ __func__ , format );
548+ break ;
549+ }
550+
551+ mtk_regmap_update_bits (afe -> regmap , memif -> data -> hd_reg ,
552+ 1 , hd_audio , memif -> data -> hd_shift );
553+
554+ mtk_regmap_update_bits (afe -> regmap , memif -> data -> hd_align_reg ,
555+ 1 , hd_align , memif -> data -> hd_align_mshift );
556+
557+ return 0 ;
558+ }
559+ EXPORT_SYMBOL_GPL (mtk_memif_set_format );
560+
561+ int mtk_memif_set_pbuf_size (struct mtk_base_afe * afe ,
562+ int id , int pbuf_size )
563+ {
564+ const struct mtk_base_memif_data * memif_data = afe -> memif [id ].data ;
565+
566+ if (memif_data -> pbuf_mask == 0 || memif_data -> minlen_mask == 0 )
567+ return 0 ;
568+
569+ mtk_regmap_update_bits (afe -> regmap , memif_data -> pbuf_reg ,
570+ memif_data -> pbuf_mask ,
571+ pbuf_size , memif_data -> pbuf_shift );
572+
573+ mtk_regmap_update_bits (afe -> regmap , memif_data -> minlen_reg ,
574+ memif_data -> minlen_mask ,
575+ pbuf_size , memif_data -> minlen_shift );
576+ return 0 ;
577+ }
578+ EXPORT_SYMBOL_GPL (mtk_memif_set_pbuf_size );
579+
364580MODULE_DESCRIPTION ("Mediatek simple fe dai operator" );
365581MODULE_AUTHOR ("Garlic Tseng <garlic.tseng@mediatek.com>" );
366582MODULE_LICENSE ("GPL v2" );
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